Journal of Signal and Information Processing

Volume 3, Issue 1 (February 2012)

ISSN Print: 2159-4465   ISSN Online: 2159-4481

Google-based Impact Factor: 0.74  Citations  h5-index & Ranking

Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications

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DOI: 10.4236/jsip.2012.31016    6,454 Downloads   11,668 Views   Citations


The LPC “Linear Predictive Coding” algorithm is a widely used technique for voice coder. In this paper we present different implementations of the LPC algorithm used in the majority of voice decoding standard. The windowing/autocorrelation bloc is implemented by three different versions on an FPGA Spartan 3. Allowing the possibility to integrate a Microblaze processor core a first solution consists of a pure software implementation of the LPC using this core RISC processor. Second solution is a pure hardware architecture implemented using VHDL based methodology starting from description until integration. Finally, the autocorrelation core is then proposed to be implemented using hardware/software (HW/SW) architecture with the existing processor. Each architecture performances are compared for different data lengths.

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[3] Speaker identification using Neural Networks on an FPGA
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