Journal of Signal and Information Processing

Volume 3, Issue 1 (February 2012)

ISSN Print: 2159-4465   ISSN Online: 2159-4481

Google-based Impact Factor: 0.74  Citations  h5-index & Ranking

Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications

HTML  Download Download as PDF (Size: 770KB)  PP. 122-129  
DOI: 10.4236/jsip.2012.31016    6,454 Downloads   11,668 Views   Citations

ABSTRACT

The LPC “Linear Predictive Coding” algorithm is a widely used technique for voice coder. In this paper we present different implementations of the LPC algorithm used in the majority of voice decoding standard. The windowing/autocorrelation bloc is implemented by three different versions on an FPGA Spartan 3. Allowing the possibility to integrate a Microblaze processor core a first solution consists of a pure software implementation of the LPC using this core RISC processor. Second solution is a pure hardware architecture implemented using VHDL based methodology starting from description until integration. Finally, the autocorrelation core is then proposed to be implemented using hardware/software (HW/SW) architecture with the existing processor. Each architecture performances are compared for different data lengths.

Cite this paper

Cited by

[1] Optimization and performance evaluation of graphic processing units for voice processing
Journal of Algorithms & Computational Technology, 2017
[2] Evaluation of Features Extraction Algorithms for a Real-Time Isolated Word Recognition System
International Journal of Electrical, Electronic Science and Engineering, 2013
[3] Speaker identification using Neural Networks on an FPGA
Electronics, Robotics and Automotive Mechanics Conference (CERMA), 2012 IEEE Ninth. IEEE, 2012

Copyright © 2020 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.