has been cited by the following article(s):
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[1]
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Gate engineering solutions to mitigate short channel effects in a 20 nm MOSFET
e-Prime - Advances in Electrical Engineering, Electronics and Energy,
2025
DOI:10.1016/j.prime.2025.100934
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[2]
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Fin-FET Enabled High-Speed PLL Design for Low Power Applications
IETE Journal of Research,
2025
DOI:10.1080/03772063.2025.2470364
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[3]
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Gate engineering solutions to mitigate short channel effects in a 20 nm MOSFET
e-Prime - Advances in Electrical Engineering, Electronics and Energy,
2025
DOI:10.1016/j.prime.2025.100934
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[4]
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Design Guidelines for Low Power Embedded Systems using Low Power Electronics
WSEAS TRANSACTIONS ON ELECTRONICS,
2023
DOI:10.37394/232017.2023.14.8
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[5]
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Doped Graphene on Silicon Bottom Gated FET for High Drain Current and Applications in RF And Logic Circuits
2022 13th International Conference on Information and Communication Technology Convergence (ICTC),
2022
DOI:10.1109/ICTC55196.2022.9952777
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