|
[1]
|
A study of emerging semi-conductor devices for memory applications
|
|
2021 |
|
|
|
|
[2]
|
NOVEL LOW POWER HALF-SUBTRACTOR USING AVL WITH SLEEP TRANSISTOR TECHNIQUE BASED ON 0.18 µM CMOS TECHNOLOGY
|
|
International Journal of Modern Trends in Engineering Science,
2018 |
|
|
|
|
[3]
|
Implementation of Static RAM with Sleep Transistor to Leakage Power Reduction
|
|
International Journal of Contemporary Technology and Management,
2017 |
|
|
|
|
[4]
|
Low Leakage Asynchronous PP based Single Ended 8T SRAM bit-cell at 45nm CMOS Technology
|
|
2016 |
|
|
|
|
[5]
|
模拟集成电路设计实训.
|
|
Research & Exploration in Laboratory,
2015 |
|
|
|
|
[6]
|
Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants
|
|
International Journal of Computer Applications,
2015 |
|
|
|
|
[7]
|
A Roadmap on the Low Power Static Random Access Memory Design Topologies
|
|
J Yadav, T Goswami, P Bhatnagar, S Birla, NK Shukla - ijser.org,
2014 |
|
|
|
|
[8]
|
Evaluation of microscopy as a field laboratory test for diagnosis of Johne's disease in farm animals.
|
|
Intas Polivet,
2014 |
|
|
|
|
[9]
|
Design a Low Power Half-Subtractor Using AVL Technique Based on 65nm CMOS Technology
|
|
International Journal of Advanced Research in Computer Engineering & Technology (IJARCET),
2013 |
|
|
|
|
[10]
|
Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology
|
|
International Journal of Computer Applications? ,
2013 |
|
|
|
|
[11]
|
Effect of Supply Voltage on Ability and Stability in IP3 SRAM Bit-Cell at 45nm CMOS Technology using N-Curve
|
|
International Journal of Computer Applications,
2013 |
|
|
|
|
[12]
|
Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications
|
|
Journal of Semiconductors,
2012 |
|
|
|
|
[13]
|
Analysis of Subthreshold Leakage Current in IP 3 SRAM Bit-Cell under Temperature Variations in Deep-Submicrometer CMOS Technology
|
|
International Journal of Computer Applications,
2012 |
|
|
|
|
[14]
|
Analysis of Gate Leakage Current in IP3 SRAM Bit-Cell under Temperature Variations in DSM Technology
|
|
parameters,
2012 |
|
|
|
|
[15]
|
Implementation of high performance and low leakage half subtractor circuit using AVL technique
|
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Information and Communication Technologies (WICT), 2012 World Congress on. IEEE, 2012.,
2012 |
|
|
|
|
[16]
|
An Analysis of Power and Stability in 6T, NC, Asymmetric, PP, and P3SRAM Bit-Cells Topologies in 45nm CMOS Technology
|
|
International Journal of Computer Applications,
2012 |
|
|
|
|
[17]
|
Analysis and Simulation of Subthreshold Leakage Current Reduction in IP3 SRAM Bit-Cell at 45 nm CMOS Technology for Multimedia Applications
|
|
M Pattanaik, NK Shukla, RK Singh - ijcte.org,
2011 |
|
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