Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
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"Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology"
written by Shilpi Birla, Neeraj Kumar Shukla, Kapil Rathi, Rakesh Kumar Singh, Manisha Pattanaik,
published by Circuits and Systems, Vol.2 No.4, 2011

has been cited by the following article(s):

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[1]	Embracing Low-Power Systems with Improvement in Security and Energy-Efficiency
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[2]	A Review on Enhancement of SRAM Memory Cell
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[3]	Performance Analysis of 8T FinFET SRAM Bit-Cell for Low-power Applications
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[4]	An 8T SRAM Cell with Improved ION/IOFF Ratio and with Faster Read Speed.
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[5]	CMOS Receiver Design for 802.11 ac Standard Using Offline Calibrated Active Inductor Based Band Pass Filter in 90 nm Technology
	2019

[6]	New High Performance 8T SRAM Cell Using Finfet Technology
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[7]	Reliability and Uniformity Enhancement in 8T-SRAM based PUFs operating at NTC
	ISLPED 2018 Proceedings of the International Symposium on Low Power Electronics and Design, 2018

[8]	Subthreshold FinFET SRAM at 20nm Technology with Improved Stability and Lower Leakage Power
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[9]	Improve Performance Static Random Access Memory Based on Design PLPSRAM
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[10]	A Survey of Design Low Power Static Random Access Memory
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[11]	Study of variability performance of CMOS active inductors
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[12]	A Novel 8T SRAM Cell using 16 nm FinFET Technology
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[13]	6 GHz RF CMOS Active Inductor Band Pass Filter Design and Process Variation Detection
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[14]	Static noise margin and power dissipation analysis of various SRAM topologies
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[15]	IO Standard Based Green Multiplexer Design and Implementation on 40nm FPGA
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[16]	Drive Strengh and LVCMOS Based Dynamic Power Reduction of ALU on FPGA
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[17]	Low voltage DCI based low power VLSI circuit implementation on FPGA
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[18]	IO Standard Based Green Multiplexer Design and Implementation on FPGA
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[19]	Clock Gated Low Power Memory Implementation on Virtex-6 FPGA
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[20]	Capacitance Based Low Power ALU Design and Implementation on 28nm FPGA
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[1]	Designing 10T SRAM for noise and Leakage Power Reduction using Stack Transistor Technique – A Review International Journal of Advanced Research in Science, Communication and Technology, 2022 DOI:10.48175/IJARSCT-3520

[2]	Performance Analysis of 8T FinFET SRAM Bit-Cell for Low-power Applications 2020 5th International Conference on Computing, Communication and Security (ICCCS), 2020 DOI:10.1109/ICCCS49678.2020.9277237

[3]	Reliability and Uniformity Enhancement in 8T-SRAM based PUFs operating at NTC Proceedings of the International Symposium on Low Power Electronics and Design, 2018 DOI:10.1145/3218603.3218642

[4]	Reliability and Uniformity Enhancement in 8T-SRAM based PUFs operating at NTC Proceedings of the International Symposium on Low Power Electronics and Design, 2018 DOI:10.1145/3218603.3218642

[5]	Study of variability performance of CMOS active inductors Microsystem Technologies, 2017 DOI:10.1007/s00542-017-3693-1

[6]	Drive Strength and LVCMOS Based Dynamic Power Reduction of ALU on FPGA Lecture Notes on Information Theory, 2013 DOI:10.12720/lnit.1.1.60-63

[7]	Low voltage DCI based low power VLSI circuit implementation on FPGA 2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES, 2013 DOI:10.1109/CICT.2013.6558076

[8]	Clock Gated Low Power Memory Implementation on Virtex-6 FPGA 2013 5th International Conference on Computational Intelligence and Communication Networks, 2013 DOI:10.1109/CICN.2013.90

[9]	IO Standard Based Green Multiplexer Design and Implementation on FPGA 2013 5th International Conference on Computational Intelligence and Communication Networks, 2013 DOI:10.1109/CICN.2013.94

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