Author(s)

V. Prasannamoorthy¹, P. Sundaramoorthi², Merin Jacob²

¹Government College of Technology, Coimbatore, Tamil Nadu, India.
²Department of Electrical and Electronics Engineering, Nehru College of Engineering and Research Centre, Thrissur, India.

As the demand for high voltage, high power inverters are increasing and there is a problem of connecting a power semiconductor switch directly to a high voltage network. As a part of this the multilevel inverters had been introduced. As a part of this, several researches had been done for the development of multilevel inverters. The commercially available and extensively studied topologies for multilevel voltage output are Neutral Point Clamped (NPC), Cascaded Half Bridge (CHB) and Flying Capacitor (FC) converters. However, with these existing topologies, there is a significant increase in the number of power switches and passive components. Thus it leads to more complex control circuitry and overall cost of the system increase with increase in the output levels. In this paper, a novel multilevel inverter is proposed in which it employs additive and subtractive topology to get higher output levels. This approach significantly reduces the number of power switches needed as compared to existing topology. The present developed multilevel inverter can generate only five voltage levels. With this proposed topology the multilevel inverter can be modified to nine-level inverter. Moreover modified hybrid multicarrier Pulse Width Modulation (PWM) technique can be implemented in the proposed multilevel inverter in order to obtain uniform switch utilization and lower THD. An appropriate modulation scheme is presented and also the proposed concept is analyzed through simulation studies.

Multilevel Inverter (MLI), Pulse Width Modulation (PWM), Multicarrier PWM Scheme, Additive and Subtractive Topology, Total Harmonic Distortion (THD)

Prasannamoorthy, V. , Sundaramoorthi, P. and Jacob, M. (2016) A Novel Multilevel Inverter Employing Additive and Subtractive Topology. Circuits and Systems, 7, 2425-2436. doi: 10.4236/cs.2016.79209.