Dr. Randy W. Mann

Globalfoundries, USA

Email: rwm3p@virginia.edu

Qualifications

2010 Ph.D., University of Virginia, Electrical Engineering

1979 B.Sc., University of North Carolina, Chemistry

Publications(selected)

1. T. B. Hook, M. Breitwisch, J. Brown, P. Cottrell, D. Hoyniak, C. Lam, and R. Mann, “Noise margin and leakage in ultra-low leakage sram cell design,”IEEE Transactions on Electron Devices, vol. 49, no. 8, pp. 1499–1501, 2002.
2. T. B. Hook, J. S. Brown, M. Breitwisch, D. Hoyniak, and R. Mann, “High-performance logic and high-gain analog cmos transistors formed by a shadow-mask technique with a single implant step,” IEEE Transactions on Electron Devices, vol. 49, no. 9, pp. 1623–1627, 2002.
3. T. B. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, and R. Mann, “Lateral ion implant straggle and mask proximity effect,”IEEE Transactions on Electron Devices, vol. 50, no. 9, pp. 1946–1951, 2003.
4. R. W. Mann, W. Abadeer, M. Brietwisch, O. Bula, J. Brown, B. Colwill, P.Cottrell, W. Crocco, S. Furkay, M. Hauser, T. Hook, D. Hoyniak, J. Johnson, C. Lam, R. Mih, J. Rivard, A. Moriwaki, E. Phipps, C. Putnam, B. Rainey, J. Toomey, M. Younus, “Ultralow-power SRAM technology,” IBM Journal of Research and Development, vol. 47, pp. 553–566, 2003.
5. Z. Luo, A. Steegen, M. Eller, R. Mann, C. Baiocco, P. Nguyen, L. Kim, M. Hoinkis, V. Ku, V. Klee, F. Jamin, P. Wrschka, P. Shafer, W. Lin, S. Fang, W. Tan, D. Park, R. Mo, J. Lian, D. Vietzke, C. Coppock, A. Vayshenker, T. Hook, V. Chan, K. Kim, A. Cowley, S. Kim, E. Kaltalioglu, B. Zhang, S. Marokkey, Y. Lin, M. Weybright, R. Rengarajan, J. Ku, T. Schiml, J. Sudijono, I. Yang, Clement Wann, “High Performance and Low Power Transistors Integrated in 65nm Bulk CMOS Technology” , in Proc. IEDM Technical Digest Electron Devices Meeting IEEE International, 2004, pp. 661–664.
6. W. C. Natzle, D. Horak, S. Deshpande, C.-F. Yu, J. C. Liu, R. W. Mann, B. Doris, H. Hanafi, J. Brown, A. Sekiguchi, M. Tomoyasu, A. Yamashita, D. Prager, M. Funk, P. Cottrell, F. Higuchi, H. Takahashi, M. Sendelbach, E. Solecky, W. Yan, L. Tsou, Q. Yang, J. P. Norum, and S. S. Iyer, “Trimming of hard-masks by gaseous chemical oxide removal (cor) for sub-10 nm gates/fins, for gate length control and for embedded logic,” in Proc. IEEE Conference and Workshop Advanced Semiconductor Manufacturing ASMC ’04, 2004, pp. 61–65.
7. A. Bhavnagarwala, S. Kosonocky, C. Radens, K. Stawiasz, R. Mann, Q. Ye, K. Chin, “Fluctuation Limits & Scaling Opportunities for CMOS SRAM Cells” , in Proc. IEDM Technical Digest Electron Devices Meeting IEEE International, 2005, pp. 659–662.
8. A. Steegen, R. Mo, R. Mann, M. C. Sun, M. Eller, G. Leake, D. Vietzke, A. Tilke, F. Guarin, A. Fischer, T. Pompl, G. Massey, A. Vayshenker, W. L. Tan, A. Ebert, W. Lin, W. Gao, J. Lian, J. P. Kim, P. Wrschka, J. H. Yang, A. Ajmera, R. Knoefler, Y. W. Teh, F. Jamin, J. E. Park, K. Hooper, C. Griffin, P. Nguyen, V. Klee, V. Ku, C. Baiocco, G. Johnson, L. Tai, J. Benedict, S. Scheer, H. Zhuang, V. Ramanchandran, G. Matusiewicz, Y. H. Lin, Y. K. Siew, F. Zhang, L. S. Leong, S. L. Liew, K. C. Park, K. W. Lee, D. H. Hong, S. M. Choi, E. Kaltalioglu, S. O. Kim, M. Naujok, M. Sherony, A. Cowley, A. Thomas, J. Sudijohno, T. Schiml, J. H. Ku, and I. Yang, “65nm cmos technology for low power applications,” in Proc. IEDM Technical Digest Electron Devices Meeting IEEE International, 2005, pp. 64–67.
9. C. Wann, R. Wong, D. J. Frank, R. Mann, S.-B. Ko, P. Croce, D. Lea, D. Hoyniak, Y.-M. Lee, J. Toomey, M. Weybright, and J. Sudijono, “SRAM cell design for stability methodology,” in Proc. (VLSI-TSA-Tech) VLSI Technology 2005 IEEE VLSI-TSA International Symposium on, 2005, pp. 21–22.
10. B. H. Calhoun, S. Khanna, R. Mann, and J. Wang, “Sub-threshold circuit design with shrinking CMOS devices,” in Proc. IEEE International Symposium on Circuits and Systems ISCAS 2009, May 24 2009–Yearly 27 2009, pp. 2541–2544.
11. R.W.Mann, S.Nalam, J.Wang, B.H.Calhoun, “Limits of Bias Based Assist Methods in Nano- Scale 6T SRAM” in: Proc. 11th International Symposium on Quality Electronic Design, ISQED’10’, 2010, pp.1–6.
12. R.W.Mann, S.Nalam, S.Khanna, J.Wang, G.Braceras, H.Pilo, B.H.Calhoun, “Impact of circuit assist methods on margin and performance in 6T SRAM” accepted for publication in the Journal of Solid State Electronics June 2010.
13. Jiajing Wang, Satyanand Nalam, Zhenyu(Jerry) Qi, Randy W. Mann, Mircea Stan, and Benton H. Calhoun, “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, accepted for publication in the CICC 2010.
14. R.W.Mann, “Interactions of technology and design in nanoscale SRAM”, Ph. D. Thesis in Electrical Engineering, University of Virginia.
15. R. W. Mann, T. B. Hook, P. T. Nguyen, B. H. Calhoun , "Nonrandom Device Mismatch Considerations in Nanoscale SRAM," , IEEE Transactions on Very Large Scale Integration (VLSI) Systems, approved for publication 5/12/2011.
16. Stuart N. Wooters, Adam C. Cabe, Zhenyu Qi, Wang J, Randy W. Mann, Benton H. Calhoun, Mircea R. Stan, Travis N. Blalock, “Tracking On-Chip Age Using Distributed, Embedded Sensors” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, approved for publication 9/3/2011.

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