Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits


The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.

Share and Cite:

A. Rjoub, A. Alajlouni and H. Almanasrah, "Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits," Circuits and Systems, Vol. 4 No. 2, 2013, pp. 123-136. doi: 10.4236/cs.2013.42018.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] K. Bard, B. Dewey, M.-T. Hsu, T. Mitchell, K. Moody, V. Rao, R. Rose, J. Soreff and S. Washburn, “Transistor Level Tools for High-End Processor Custom Circuit De sign at IBM,” IEEE Proceedings of the Journal, Vol. 95, No. 3, 2007, pp. 530-554. doi:10.1109/JPROC.2006.889385
[2] Z. T. Li and S. M. Chen, “Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Swi tching,” IEEE Proceedings of 10th Computer-Aided De sign and Computer Graphics, Beijing, October 2007, pp. 315-320.
[3] C. H. Chen, X. J. Yang and M. Sarrafzadeh, “Potential Slack: An Effective Metric of Combinational Circuit Per formance,” IEEE International Conference on Computer Aided Design, San Jose, 5-9 November 2000, pp. 198-201.
[4] M. Naresh and S. Sachin, “Timing Analysis and Optimi zation of Sequential Circuits,” Kluwer Acadimic Publi sher Group, 1999.
[5] F. Sill and F. G. D. Timmermann, “Total Leakage Power Optimization with Improved Mixed Gates,” Proceedings of the 18th Symposium on Integrated Circuits and System Design, Florianolpolis, 4-7 September 2005, pp. 154-159.
[6] R. Nair, C. L. Berman, P. S. Hauge and E. J. Yoffa, “Ge neration of Performance Constraints for Layout,” IEEE Transactions on Computer-Aided Design, Vol. 8, No. 8, 1989, pp. 860-874. doi:10.1109/43.31546
[7] T. Gao, P. M. Vaidya and C. L. Liu, “A New Perfor mance Driven Placement Algorithm,” Proceedings of IEEE International Conference on Computer Aided Design, Santa Clara, 11-14 November 1991, pp. 44-47.
[8] H. Youssef and E. Shragowitz, “Timing Constraints for Correct Performance,” IEEE Proceedings of International Conference on Computer Aided Design, Santa Clara, 11 15 November 1990, pp. 24-27.
[9] S. Dutta, S. Nag and K. Roy, “ASAP: A Transistor Sizing Tool for Speed, Area, and Power Optimization of Static CMOS Circuits,” International Symposium of Circuits and Systems, London, 30 May-2 June 1994, pp. 61-64.
[10] H.-Y. Song, K. Nepal, R. I. Bahar and J. Grodstein “Timing Analysis for Full-Custom Circuits Using Sym bolic DC Formulations,” IEEE Transactions on Com puter-Aided Design Integral Circuits Systems, Vol. 25, No. 9, 2006, pp. 1815-1830.
[11] K. S. Hedlund, “Aesop: A Tool for Automated Transistor Sizing,” Proceedings of the 24th ACM/IEEE conference on Design automation, Miami Beach, 28 June-1 July 1987, pp. 114-120.
[12] U. Seckin and C.-K. K. Yang, “A Comprehensive Delay Model for CMOS CML Circuits,” IEEE Transactions on Circuits and Systems I, Vol. 55, No. 9, 2008, pp. 2608-2618. doi:10.1109/TCSI.2008.920069
[13] B., J. Hansen and K. Cameron, “A Determinis tic Algorithm for Automatic CMOS Transistor Sizing,” IEEE Proceedings of Conference on Custom Integmted Circuits Conference, Portland, 4-7 May 1987, pp. 421-424.
[14] S. Raja, F. Varadi, M. Becer and J. Geada, “Transistor Level Gate Modeling for Accurate and Fast Timing, Noise, and Power Analysis,” Proceedings of Design Automation Conference, Anaheim, 8-13 June 2008.
[15] R. Rogenmoser and Kaeslin, “The Impact of Transistor Sizing on Power Efficiency in Submicron CMOS Cir cuits,” IEEE Journal of Solid-State Circuits and systems, Vol. 32, No. 7, 1997, pp. 1142-1145.
[16] W. Yang and M. Dunga, Eds., “BSIM4.6.1 MOSFET Model, User Manual,” 2008. http://www.devices.eecs.berkely.edy/~bsim3/bsim4.html
[17] D. Blaauw, K. Chopra, A. Srivastava and L. Scheffer, “Statistical Timing Analysis: From Basic Principles to State of the Art,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 4, 2008, pp. 589-607. doi:10.1109/TCAD.2007.907047
[18] A. Jain and D. Blaauw, “Slack Borrowing in Flip-Flop Based Sequential Circuits,” Proceedings of the 15th ACM/ IEEE Great Lakes Symposium on VLSI, Chicago, 17-19 April 2005, pp. 96-101.
[19] A. Dendouga, N. Bouguechal, S. Barra and O. Manck, “Timing Characterization and Layout of a Low Power Differential C2MOS Flip-Flop in 0.35 μm Technology,” 2nd International Conference on Electrical Engineering Design and Technologies, Hammamet, 8-10 November 2008, pp. 1-4.
[20] P. Y. Calland, A. Mignotte, O. Peyran, Y. Robert and F. Vivien, “Retiming DAG’s (Direct Acyclic Graph),” IEEE Transaction on Computer-Aided Design Integrated Cir cuits and Systems, Vol. 17, No. 12, 1998, pp. 1319-1325. doi:10.1109/43.736571
[21] K. Choi and A. Chatterjee, “PA-ZSA (Power Aware Zero Slack Algorithm): A Graph Based Timing Analysis for Ultra Low-Power CMOS VLSI,” Proceedings of the Power and Timing Modeling, Optimization and Simula tion, Seville, 11-13 September 2002, pp. 178-187.
[22] C.-P. R. Liu and J. A. Abraham, “Transistor Level Syn thesis for Static CMOS Combinational Circuits,” Ninth Great Lakes Symposium on VLSI, Austin, 4-6 March 1999, pp. 172-175,
[23] Nanoscale Integration and Modeling (NIMO) Group, Pre dictive Technology Model (PTM), 2008.
[24] A. Rjoub and A. B. Alajlouni, “Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits,” IEEE Proceedings of the 16th Mediterranean Electrotechnical, Yasmine Hammamet, 25-28 March 2012, pp. 80-83.

Copyright © 2024 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.