On the Operation of CMOS Active-Cascode Gain Stage

DOI: 10.4236/jcc.2013.16004   PDF   HTML     4,766 Downloads   7,101 Views   Citations

Abstract

An s-domain analysis of the full dynamics of the pole-zero pair (frequency doublet) associated with the broadly used CMOS active-cascode gain-enhancement technique is presented. Quantitative results show that three scenarios can arise for the settling behavior of a closed-loop active-cascode operational amplifier depending on the relative locations of the unity-gain frequencies of the auxiliary and the main amplifiers. The analysis also reveals that, although theoretically possible, it is practically difficult to achieve an exact pole-zero cancellation. The analytical results presented here provide theoretical guidelines to the design of CMOS operational amplifiers using this technique.

Share and Cite:

Chiu, Y. (2013) On the Operation of CMOS Active-Cascode Gain Stage. Journal of Computer and Communications, 1, 18-24. doi: 10.4236/jcc.2013.16004.

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1] B. J. Hosticka, “Improvement of the Gain of MOS Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 14, No. 6, 1979, pp. 1111-1114. http://dx.doi.org/10.1109/JSSC.1979.1051324
[2] K. Bult and G. J. G. M. Geelen, “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain,” IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, 1990, pp. 1379-1384. http://dx.doi.org/10.1109/4.62165
[3] E. Sackinger and W. Guggenbuhl, “A High-Swing, High-Impedance MOS Cascode Circuit,” IEEE Journal of Solid-State Circuits, Vol. 25, No. 1, 1990, pp. 289-298. http://dx.doi.org/10.1109/4.50316
[4] H. C. Yang and D. J. Allstot, “An Active-Feedback Cascode Current Source,” IEEE Transactions on Circuits and Systems, Vol. 37, No. 5, 1990, pp. 644-646. http://dx.doi.org/10.1109/31.55008
[5] P. R. Gray and R. G. Meyer, “MOS Operational Amplifier design—A Tutorial Overview,” IEEE Journal of Solid-State Circuits, Vol. 17, No. 6, 1982, pp. 969-982. http://dx.doi.org/10.1109/JSSC.1982.1051851
[6] A. A. Abidi, “On the Operation of Cascode Gain Stages,” IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, 1988, pp. 1434-1437. http://dx.doi.org/10.1109/4.90043
[7] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, “Analysis and Design of Analog Integrated Circuits,” 4th Edition, Wiley, New York, 2001.
[8] K. Bult, “EE215A Course Notes,” UCLA, 1996.
[9] F. D. Waldhauer, “Analog Integrated Circuits of Large Bandwidth,” IEEE International Convention Record, Vol. 11, Part 2, 1963, pp. 200-207.
[10] P. R. Gray and R. G. Meyer, “Recent Advances in Monolithic Operational Amplifier Design,” IEEE Transactions on Circuits and Systems, Vol. 21, No. 3, 1974, pp. 317-327. http://dx.doi.org/10.1109/TCS.1974.1083851
[11] B. Y. T. Kamath, R. G. Meyer and P. R. Gray, “Relationship between Frequency Response and Settling Time of Operational Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 9, No. 6, 1974, pp. 347-352. http://dx.doi.org/10.1109/JSSC.1974.1050527

  
comments powered by Disqus

Copyright © 2020 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.