A Reconfigurable Network-on-Chip Datapath for Application Specific Computing

DOI: 10.4236/cs.2013.42025   PDF   HTML     5,072 Downloads   7,292 Views   Citations


This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC topologies and parameters are investigated with standard benchmark programs, including fine grain and coarse grain computations. Simulation results highlight the flexibility and scalability of the proposed polymorphic NoC processor for a wide range of application domains.

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J. Weber and E. Oruklu, "A Reconfigurable Network-on-Chip Datapath for Application Specific Computing," Circuits and Systems, Vol. 4 No. 2, 2013, pp. 181-192. doi: 10.4236/cs.2013.42025.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] “International Technology Roadmap for Semiconductors,” 2009. http://www.itrs.net/Links/2009ITRS/Home2009.htm
[2] D. Hentrich, E. Oruklu and J. Saniie, “Polymorphic Computing: Definition, Trends, and a New Agent-Based Architecture,” Circuits and Systems, Vol. 2, No. 4, 2011, pp. 358-364. doi:10.4236/cs.2011.24049
[3] J. Weber, E. Oruklu and J. Saniie, “Architectural Topologies for NoC Datapath Polymorphic Processors,” IEEE International Conference on Electro/Information Technology, Mankato, 15-17 May 2011, pp. 1-6.
[4] K. Compton and S. Hauck, “Reconfigurable Computing: A Survey of Systems and Software,” ACM Computing Surveys, Vol. 34, No. 2, 2002, pp. 171-210. doi:10.1145/508352.508353
[5] Z. Guo, W. Najjar, F. Vahid and K. Vissers, “A Quantitative Analysis of the Speedup Factors of FPGAs over Processors,” FPGA Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, New York, 2004, pp. 162-170.
[6] K. Underwood, “FPGAs vs CPUs: Trends in Peak Floating-Point Performance,” FPGA Proceedings of the ACM/ SIGDA 12th International Symposium on Field Programmable Gate Arrays, New York, 2004, pp. 171-180.
[7] T. Todman, G. Constantinides, S. Wilton, O. Mencer, W. Luk and P. Cheung, “Reconfigurable Computing: Architectures and Design Methods,” IEEE Proceedings of Computers and Digital Techniques, Vol. 152, No. 2, 2005, pp. 193-207.
[8] R. Cheung, N. Telle, W. Luk and P. Cheung, “Customizable Elliptic Curve Cryptosystems,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 13, No. 9, 2005, pp. 1048-1059.
[9] P. Baglietto, M. Maresca and M. Migliardi, “Euclidean Distance Transform on Polymorphic Processor Array,” CAMP Proceedings of Computer Architectures for Ma chine Perception, Como, 18-20 September 1995, pp. 288-293.
[10] G. Kuzmanov and W. van Oijen, “Floating-Point Matrix Multiplication in a Polymorphic Processor,” ICFPT In ternational Conference on Field-Programmable Technology, Kitakyushu, 12-15 December 2007, pp. 249-252.
[11] S. Chai, S. Chiricescu, R. Essick, B. Lucas, P. May, K. Moat, J. Norris, M. Schuette and A. Lopez-Lagunas, “Streaming Processors for Next Generation Mobile Imaging Applications,” Communications Magazine, Vol. 43, No. 12, 2005, pp. 81-89. doi:10.1109/MCOM.2005.1561924
[12] H. Hubert and B. Stabernack, “Profiling-Based Hardware/ Software Coexploration for the Design of Video Coding Architectures,” IEEE Transactions on Circuits and Sys tems for Video Technology, Vol. 19, No. 11, 2009, pp. 1680-1691. doi:10.1109/TCSVT.2009.2031522
[13] C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold and M. Gokhale, “The Napa Adaptive Processing Architecture,” IEEE Symposium on Proceedings of FPGAs for Custom Computing Machines, 17 April 1998, pp. 28-37.
[14] S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov and E. Panainte, “The Molen Polymorphic Processor,” IEEE Transactions on Computers, Vol. 53, No. 11, 2004, pp. 1363-1375. doi:10.1109/TC.2004.104
[15] N. Vassiliadis, G. Theodoridis and S. Nikolaidis, “The Arise Approach for Extending Embedded Processors with Arbitrary Hardware Accelerators,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 17, No. 2, 2009, pp. 221-233.
[16] M. Gokhale and J. Stone, “NAPA C: Compiling for a Hybrid Risc/Fpga Architecture,” IEEE Symposium on Proceedings of FPGAs for Custom Computing Machines, 17 April 1998, pp. 126-135.
[17] J. Cong, G. Han and Z. Zhang, “Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 9, 2006, pp. 986-997.
[18] S. Gupta, N. Dutt, R. Gupta and A. Nicolau, “SPARK: A High-Level Synthesis Framework for Applying Parallelizing Compiler transformations,” Proceedings of the 16th International Conference on VLSI Design, New Delhi, 4-8 January 2003, pp. 461-466.
[19] The SPARC Architecture Manual, Version 8, Sun Micro systems, 1992. http://www.sparc.org/standards/V8.pdf
[20] Ns-2, The Network Simulator. http://nsnam.isi.edu/nsnam/index.php/Main_Page
[21] M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge and R. Brown, “Mibench: A Free, Commercially Representative Embedded Benchmark Suite,” IEEE Interna tional Workshop on Workload Characterization, Decem ber 2001, pp. 3-14.

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