An Enhanced Bulk-Driven Folded-Cascode Amplifier in 0.18 µm CMOS Technology

Arash Ahmadpour, Pooya Torkzadeh

Department of Electronic Engineering, Islamic Azad University, Lahijan Branch, Lahijan, Iran.
Department of Electronic Engineering, Islamic Azad University, Science and Research Branch, Tehran, Iran.

DOI: 10.4236/cs.2012.32025                

Abstract

A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the conventional structure. Settling behavior of proposed amplifier is also improved and accuracy more than 8 bit for 500 mV voltage swing is obtained. Simulation results using HSPICE Environment are included which validate the theoretical analysis. The amplifier is designed using standard 0.18 μm CMOS triple-well (level 49) process with supply voltage of 1.2 V. The correct functionality of this configuration is verified from –50℃ to 100℃.

Keywords

Bulk-Driven Folded-Cascode (BDFC) Amplifier; DC-Gain; Bulk-Driven (BD); Folded-Cascode (FC); CMOS

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	S. Chatterjee, Y. Tsvidis and P. Kinget, “Ultra-Low Voltage Analog Integrated Circuits,” IEICE Transactions on Electronics, Vol. E89-C, No. 6, 2006, pp. 673-680.
[2]	S. Yan and E. Sanchez-Sinencio, “Low-Voltage Analog Circuit Design Techniques: A Tutorial,” IEICE Transactions, Vol. E00-A, No. 2, 2000, pp. 179-196.
[3]	J. Ramirez-Angulo, R. G Carvajal and A. Torralba, “Low Supply Voltage High Performance CMOS Current Mirror with Low Input and Output Voltage Requirements,” IEEE Transactions on Circuits and Systems-II Express Briefs, Vol. 51, No. 3, 2004, pp. 124-129. doi:10.1109/TCSII.2003.822429
[4]	ITRS, “The International Technology Roadmap for Semconductors,” 2008. http://public.itrs.net
[5]	B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw Hill, New York, 2001.
[6]	P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, “Analysis and Design of Analog Integrated Circuits,” 4th Edition, John Wiley & Sons, New York, 2001.
[7]	S. M. R. Hasan and N. Ula, “A Novel Feed-Forward Compensation Technique for Single-Stage Fully-Differential CMOS Folded-Cascode Rail-to-Rail Amplifier,” Electrical Engineering, Vol. 88, No. 6, 2006, pp. 509-517. doi:10.1007/s00202-005-0306-2
[8]	B. Alizadeh and A. Dadashi, “An Enhanced Folded-Cascode Op-Amp in 0.18 μm CMOS Process with 67 dB DC-Gain,” IEEE International Conference, Faible Tension Faible Consummation, 30 May-1 June 2011, pp. 87-90.
[9]	J. Rosenfeld, M. Kozak and E. G. Friedman “A BulkDriven CMOS OTA with 68-dB DC-Gain,” Proceedings of IEEE International Electronics Circuits Systems, TelAviv, 13-15 December 2004, pp. 5-8.
[10]	M. Trakimas and S. Sonkusale, “A 0.5 V Bulk-Input OTA with Improved Common-Mode Feedback for Low-Frequency Filtering Applications,” Analog Integrated Circuits and Signal Processing, April 2009, Vol. 59, No. 1, pp. 83-89. doi:10.1007/s10470-008-9236-z
[11]	R. Assaad and J. Silva-Martinez, “Enhancing General Performance of Folded-Cascode Amplifier by Recycling Current,” Electronics Letters, Vol. 43, No. 23, 2007, pp. 1243-1244. doi:10.1049/el:20072031