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An 8 Bit 0.8 GS/s 8.352 mW Modified Successive Approximation Register Based Analog to Digital Converter in 65 nm CMOS

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DOI: 10.4236/cs.2015.612028    3,044 Downloads   3,359 Views  

ABSTRACT

We propose a new approach in reducing the power consumption of the successive approximation register Analog to Digital Converter (SAR-ADC) by changing the convergence algorithm of the Digital to Analog converter (DAC) input of the SAR-ADC. Different search algorithms such as binary search tree, moving binary search tree (BST), least significant bit shifter (LSB), adaptive algorithm and split-register moving BST algorithm are designed and analyzed for faster convergence of the DAC input. In this paper, we design a 0.8 GS/s, 8 bit (Effective number of bits (ENOB)—7.42), 8.352 mW SAR ADC with a proposed moving BST algorithm in 65 nm CMOS which ranks amongst the current state of the art ADCs with a FOM 65.25 fJ/step.

Conflicts of Interest

The authors declare no conflicts of interest.

Cite this paper

Parthasarathy, A. (2015) An 8 Bit 0.8 GS/s 8.352 mW Modified Successive Approximation Register Based Analog to Digital Converter in 65 nm CMOS. Circuits and Systems, 6, 280-291. doi: 10.4236/cs.2015.612028.

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