[1]
|
http://www.itrs.net/Links/2009ITRS/
|
[2]
|
http://www.intel.com/technology/mooreslaw/
|
[3]
|
C. Wassuber, H. Kosina and S. Selbertherr, “SIMON—A Simulator for Single-Electron Tunnel Devices and Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 9, 1997, pp. 937-944. Hdoi:10.1109/43.658562
|
[4]
|
R. H. Chen, “MOSES: A General Monte Carlo Simulator for Single-Electronic Circuits,” The Electrochemical Society, Vol. 96-2, 1996, p. 576.
|
[5]
|
K. Uchida, K. Matsuzawa, J. Koga, R. Ohba, S. Takagi and A. Toriumi, “Analytical Single-Electron Transistor (SET) Model for Design and Analysis of Realistic SET Circuits,” Japanese Journal of Applied Physics, Vol. 39, Part 1, No. 4B, 2000, pp. 2321-2324.
Hdoi:10.1143/JJAP.39.2321H
|
[6]
|
H. Inokawa and Y. Takahashi, “A Compact Analytical Model for Asymmetric Single-Electron Tunneling Transistors,” IEEE Transactions on Electron Devices, Vol. 50, No. 2, 2003, pp. 455-461. Hdoi:10.1109/TED.2002.808554
|
[7]
|
S. Mahapatra, V. Vaish, C. Wasshuber, K. Banerjee and A. M. Ionescu, “Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design,” IEEE Transactions on Electron Devices, Vol. 51, No. 11, 2004, pp. 1772-1782. Hdoi:10.1109/TED.2004.837369
|
[8]
|
T. Dittrich, P. H?nggie, G. L. Ingold, B. Kramer, G. Sch??n and W. Zwerger, “Quantum Transport and Dissipation,” Wiley-VCH, Berlin, 1998.
|
[9]
|
C. Delerue and M. Lanno, “Nanostructures: Theory and Modelling,” Springer, Berlin, 2004.
|
[10]
|
D. V. Averin and K. K. Likharev, “Mesoscopic Phenomena in Solids,” Elsevier, Amsterdam, 1991.
|
[11]
|
S. M. Sze and K. K. Ng, “Physics of Semiconductor Devices,” 3rd Edition, John Wiley & Sons, New Jersey, 2007.
|
[12]
|
C. Dubuc, J. Beauvais and D. Drouin, “A Nanodamascene Process for Advanced Single-Electron Transistor Fabrication,” IEEE Transactions on Nanotechnology, Vol. 7, No. 1, 2008, pp. 68-73.
|
[13]
|
A. Beaumont, C. Dubuc, J. Beauvais and D. Drouin, “A Nanodamascene Process for Advanced Single-Electron Transistor Fabrication,” IEEE Transactions on Nanotechnologyon, Vol. 7, No. 1, 2009, pp. 68-73.
doi:10.1109/TNANO.2007.91343010
|
[14]
|
C. Dubuc, A. Beaumont, J. Beauvais and D. Drouin, “Current Conduction Models in the High Temperature Single-Electron Transistor,” Solid-State Electronics, Vol. 53, No. 5, 2009, pp. 478-482.
Hdoi:10.1016/j.sse.2009.03.003
|
[15]
|
J. H. Werner and H. H. Guttler, “Barrier Inhomogeneities at Schottky Contacts,” Journal of Applied Physics, Vol. 69, No. 3, 1991, pp. 1522-1533. Hdoi:10.1063/1.347243
|