Comparative Methodical Assessment of Established MOSFET Threshold Voltage Extraction Methods at 10-nm Technology Node

Threshold voltage (VTH) is the most evocative aspect of MOSFET operation. It is the crucial device constraint to model on-off transition characteristics. Precise VTH value of the device is extracted and evaluated by several estimation techniques. However, these assessed values of VTH diverge from the exact values due to various short channel effects (SCEs) and non-idealities present in the device. Numerous prevalent VTH extraction methods are discussed. All the results are verified by extensive 2-D TCAD simulation and confirmed through analytical results at 10-nm technology node. Aim of this research paper is to explore and present a comparative study of largely applied threshold extraction methods for bulk driven nano-MOSFETs especially at 10-nm technology node along with various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented to infer the most appropriate extraction method at nanometer technology nodes.


Introduction
Incessant abridging of IC technology, together with precision of V TH control techniques and reduction in SCE, is asserting the V TH to very low values. For proper operation of MOSFET, we need to evaluate exact threshold voltage (V TH ). Perfectly appraised V TH is required to provide proper gate control over device channel conduction (see Figure 1).
The tens of millivolts miscalculation cannot be neglected as it can prompt serious er-rors in circuit functionality. Especially for robust nano-scale design of analog circuits with high speed operation, precise valuation of V TH is essential to illustrate the exact device behaviour [1] [2] [3] [4]. Device matching also depends on the estimated V TH values. V TH is frequently used for accessing and predicting device performance. It is also commonly used to check the inconsistency due to manufacturing process technological parameter fluctuations. Other applications of V TH can be listed as to evaluate reliability factors such as radiation damage, hot carrier, stress, temperature instability, ageing degradation etc.
The threshold voltage parameter is largely extracted directly from the transfer characteristics of the device. There is no critical point in the I D -V GS curve that can be recognized as threshold point due to sub-threshold leakage current. This creates vagueness in V TH estimation. The weak inversion region shows exponential deviations while strong inversion shows linear/quadratic deviations. However, the V TH is identified amid weak and strong inversion transition region [5] [6]. V TH also depends on several device parameters (Gate width, Gate Overlap, Gate length, biased bulk, temperature etc.) and process technology limitations (Cox, tox, doping concentration (NA) etc.) [7] [8]. This makes V TH estimation more challenging.
In consideration to the above, this paper presents the study and analysis of numerous V TH extraction methods at various sub 45-nm technology node. The outcomes of the analysis are implemented on a simple resistive load inverter for computing noise margins to infer the performance of various threshold voltage extraction methods at sub 45-nm technology node.
Rest of the paper is organized as follows. Section 2 categorizes several threshold voltage extraction methods on the basis of their assessment methodology. Section 3 to Section 8 discuss and evaluate the various mentioned threshold voltage extraction methods at 10-nm technology node and other sub 45-nm technology nodes. Further, Section 9 presents the tabulated compiled simulation results, comparison and discussion for various sub 45-nm technology nodes. Application of the threshold extraction methods to implement noise analysis is briefly presented in Section 10. Finally, concluding remarks

Threshold Voltage Estimation Techniques
Ideally, V TH of a device is the critical gate voltage below which the drain to source current (I D ) is zero, But practically, sub-threshold leakage current exists for V GS below V TH .
As the drain current doesn't drop abruptly to zero and hence, it becomes challenging to precisely determine the critical point at which switching of I D takes place. Due to this reason, several procedures presented in literature use diverse descriptions to extract the V TH of the MOSFET but still has a scope for improvement to correctly evaluate V TH [9] [10]. This paper revisits V TH extraction techniques and examines these for simplified square-sized NMOS device at 10-nm technology node. For precise evaluation of the methods, the process is reiterated in similar conditions on other sub 45-nm technology nodes [11] [12].
For simplicity, the threshold extraction methods have been categorized into six main groups on the basis of their assessment methodology as: 1) I D based extraction methods; 2) Derivative of I D based extraction methods; 3) Integral of I D based extraction methods; 4) Self-extraction methods; 5) Deviation based extraction methods;

6) Hybrid extraction methods.
It is considered that the threshold voltage changes with the change in the operating region of the MOSFET specifically in linear/ triode region and saturation region. Distinctive efforts are made to accurately calculate the V TH in both the operating regions [13] [14] [15]. Hence the corresponding respective values of V TH are evaluated as V LIN and V TSAT for all the discoursed methods on our test device. Figure 1 shows the basic biasing settings for n-channel MOSFET. The test device considered is a square-sized uniformly doped bulk driven n-channel nano-MOSFET with 10-nm channel length.
The source and drain regions are laterally identical with gradual doping characteristics.
Special effects were considered to extract the realistic output of the device. Figure 2 represents the transfer characteristics of our test device.

ID Based Extraction Methods
These methods use the drain current (I D ) directly in the extraction method of threshold voltage. Some common methods listed underneath are briefly discussed below.

Constant Current Source (CCM) Method
This method determines V TH as the gate voltage for an arbitrary critical drain current (I DCRITICAL ) value [16] [17]. To estimate the V TH using this method, I D versus V GS graph is plotted on a semi-logarithmic scale for two extreme values of V DS i.e. high biased and low biased. For our test device, we considered V DS = 0.9 V and V DS = 0.1 V respectively.
The I DCRITICAL is technology reliant, generally considered as (0.1 μA) × (W/L), where W and L are the gate width and gate length. (1) is designated such that V TH is on the transition point of linear-sub-threshold region of the device [11] [18] [19].

Implementation of CCM on Test Device
The technique was implemented on our test device square-sized NMOS with 10-nm technology node and was repeated in similar conditions on other sub 45-nm technology nodes. Figure 3 represents the simulated results and extraction output (V TLIN and V TSAT ) using CCM on our test device.  The outcome of the results was as follows:

Drift-Diffusion Equality (DDE) Method
Diffusion current governs the total current in sub-threshold region whereas drift current dominates in strong inversion region. This DDEM process states that by applying low drain voltage (V DS ≈ 0.1 V), the threshold voltage is the distinctive gate voltage at which the condition I DRIFT = I DIFFUSION holds true [20] [21]. Hence, statistically we can represent the threshold voltage value as: where I Drift and I Diffusion represent the drift current and diffusion current respectively.

Implementation of DDEM on Test Device
The technique was implemented on the test device.
The outcome of the result was as follows: The DDEM process has the restriction of low biased V DS = 0.1 V. Since the device is always made to operate in linear region, hence the saturation region threshold voltage V TSAT could not be calculated. Figure 4 shows the simulated results of our test device for I DRIFT and I DIFFUSION with the variation in V GS to extract the threshold voltage.

Derivative of ID Based Methods
These methods use the derivative or the higher order derivate of the drain current value in the extraction method of threshold voltage. Fundamental V TH extraction methods using this respective technique are briefly discussed below.

Linear Extrapolation (LEM) Technique
In this LEM technique, we determine the V TH of the transistor using transconductance (g m ) and I DS -V GS curve. The g m is defined as the derivative (slope) of I D -V GS relationship.
The extreme g m obtained on the I D -V GS characteristic curve is used to extrapolate the gate voltage (V GS ) as shown in Figure 5. The attained V GS is extracted V TH for the given conditions. The I D for linear region is associated with V GS as: This LEM process provides clear steps for V TH assessment but it is partial to linear region of operation i.e. for low values of V DS . Maximum g m point is not obtainable for higher values of V DS . Furthermore, the DIBL effect also comes into picture for higher V DS and diminishes effective V TH values. Apart from these issues, this method also lacks to determine a constant V TH as dissimilar methods used for attaining maximum g m values. g m also depends on SCEs such as velocity saturation, overlap variations, extrinsic resistance, channel length modulation and so on. This reliance of g m and critical point of maximum g m is tough to accurately model. Henceforth, this produces loopholes in this process to precisely evaluate the V TH .

Implementation of LEM on Test Device
The technique was implemented on the test device.
The outcome of the result was as follows: As described above, the Maximum g m is not obtainable for higher values of V DS .
Hence special efforts were made to calculate V TSAT using this method. Figure

Quadratic Extrapolation (QEM) Method
Technique named Quadratic Extrapolation Method (QEM) is also called as "Linear Extrapolation in Saturation Region". It is used to calculate threshold voltage using LEM in saturation region (V TSAT ). As mentioned in LEM, the I D for linear region is proportional to (V GS − V TH ). Similarly, I D in saturation region is proportional to (V GS − V TH ) 2 as shown in Equation (4): Hence V TSAT can be extracted by extrapolating the curve D I versus V GS at the inflexion point of the curve as shown in Figure 6.

Implementation of QEM on Test Device
The technique was implemented on the test device.
The outcome of the result was as follows:

Second-Derivative (SD) Method
The second-derivative method (SDM), formerly entitled as transconductance change method [21] [22], was developed to avoid dependence on series resistances. It evaluates V TH as the V GS value at which the derivative of the transconductance (i.e., ) is a maximum. To intricate the logic, it uses the ideal case of a simple Level = 1 MOSFET SPICE model, where I D = 0 for V G < V T , and I D is directly proportional to V G for V G > V T . With these suppositions, dI D /dV G becomes a step function, which is zero for V G < V T and is a positive constant for V G > V T . Therefore, 2 2 D G d I dV will go to infinity exactly at V G = V T . Such a simple assumption is apparently not true in a real device, and thus 2 2 D G d I dV will not turn out to be infinite at V T . However, it will exhibit a maximum value at V GS = V TH . Figure 7 shows the SDM output waveform of the test device for V TLIN extraction at constant V DS = 0.1 V.
The execution of this SDM process in the linear region is extremely sensitive to Figure 6. Extraction of V TSAT using QEM for V DS = 0.9 V. measurement error and noise, as the second derivative amounts to applying a high-pass filter to the measurement [23].

Implementation of SDM on Test Device
The technique was implemented on the test device. The process was widely affected by noise. Special possessions of filtration and smoothening of curve were considered to extract the correct output as shown in Figure 8.
The outcome of the result was as follows:

Third-Derivative (TD) Method
In this TDM process, it has been proposed that the V TH can be extracted from the value of V GS at which the third derivative of the current I D (i.e., 3 ) has a maximum value [24]. Conversely, the maxima and minima of the third derivative always fall to the left and right of the second derivative maxima, which is located at d 3 I D /dV GS 3 . Figure 9 clearly illustrates this fact. Therefore, the third derivative technique is evidently incompatible with the broadly used second derivative method. Figure 9 and Figure 10 present the application of this TDM process to the 10-nm technology node test device in the linear and saturation regions, at drain voltages of 0.1 V and 0.9 V, respectively. It is clear from these figures that the TDM technique is extremely affected by tentative noisy data. Though investigational noise could be diminished by numerical flattening techniques or by fitting the semi-empiric models, the extracted V TH value would still be irreconcilable with that extracted by the SD method.
Implementation of TDM on Test Device Figure 9. Extraction of V TLIN using TDM for V DS = 0.1 V. Figure 10. Extraction of V TSAT using TDM for V DS = 0.9 V.
The technique was implemented on the test device. The method was vastly affected by the investigational noise. Hence it was challenging to extract the threshold values.
Special properties of smoothening and filtration of the curve were considered to extract the correct output. Even after high considerations, it was observed that V TLIN value was lower than V TSAT value which is commonly unusual.
The outcome of the result was as follows:

Ghibaudo Method/Current-to-Square-Root-of-Transconductance Ratio (CsrTR) Method
The CsrTR method formerly called as Ghibaudo Method (GM) was developed to dodge the extracted V TH value dependence on mobility degradation and parasitic series resistance [25] [26] [27]. The ratio of the drain current to the square root of the transconductance, in the linear region, is given by Equation (5) as: The GM technique, also occasionally called as ''the modified Y function method'', has been freshly enhanced for application to contemporary devices using a more universal mobility degradation model.
The V TH is extracted from the intercept of the GM versus V GS linear fit. Figure 11 shows the results of applying this method to the present test device in the linear region. As can be witnessed, it is not very clear in the method from where to linearly extrapolate to find the V GS axis intercept. It does not evidently show the supposedly expected linear behavior. Therefore, the linear extrapolation shown in Figure 11 is only a guess, amidst the evident non-linearity present.

Implementation of Ghibaudo Method (GM) on Test Device
The technique was implemented on the test device. Non-linearity in the curve caused difficulties in extrapolation process to estimate the required values. Figure 12 shows the results of applying this method to the present test device in the saturation region. The outcome of the result was as follows:

Transconductance to Current Ratio (TCR) Method
This method is based on calculating TCR as the ratio of transconductance to the drain current as described in Equation (6) [28] [29]: It states that the threshold voltage can be determined as the value of V GS where TCR presents its maximum negative slope i.e. V GS corresponding to the minimum value of curve dTCR/dV GS . However, considering TCR by itself significantly increases random tentative noise, specifically in weak inversion.

Implementation of TCR Method on Test Device
The technique was implemented on the test device. The method was highly affected by the investigational noise as seen in Figure 13 and Figure    and V TSAT respectively. Hence it was challenging to extract the threshold values. Filtration and smoothening of the curve like properties were applied to extract the correct output. Even after high considerations, it was observed that V TLIN value was lower than V TSAT value which is generally unusual.
The outcome of the result was as follows:

Integral of ID Based Methods
These methods use the integral of the drain current value in the extraction method of threshold voltage. Prevalent V TH extraction methods using this technique are briefly discussed below [30] [31].

Transition Method
This TM technique was stimulated by the properties of the integral difference function D(V,I), which had been formerly defined for two-terminal device as [32]: As shown in Equation (7), this function presents the advantageous features of eradicating the effect of any linear element (resistance) coupled in series with the device. To extract V TH , the drain current is constantly measured from below the expected value of V TH versus V GS with a small constant drain voltage (V DS ≈ 100 mV). Subsequently, the succeeding function TM is numerically calculated from the measured data: where V G0 represents the lower limit of integration analogous to a gate voltage well below threshold in Equation (8). Usually chosen V G0 = 0. The logic of the method is based on the ideal case of a MOSFET, piecewise modelled as: I D = I LEAKAGE for V GS < V TH and I D is proportional to V GS for V GS > V TH . Using the previous streamlining supposition, we observe that: 1) Function TM presents a discontinuity at V TH ; 2) TM = −V GS for V GS < V TH ; and 3) TM = +V TH for V GS > V TH .
Since for a real device such simplifying conventions are apparently not precisely true, function TM will present an extreme value due to the mobility degradation and its value will be close to V TH .
A plot of TM versus V GS or ln(I D ) should result in a straight line below threshold, where the current is dominated by diffusion and is principally exponential. As soon as V GS = V TH , the function TM should vitiate due to mobility degradation. The specified logic accords with the test device as shown in Figure 15. Hence the maximum of TM approaches the V TH value of the device. The shape of the curve is swayed by the parasitic resistance and mobility degradation effects, but not significantly its maxima, lest those effects are exceedingly prominent. Hence, the parasitic series resistance consequence is not totally eradicated since a MOSFET is not a two-terminal device with node current as I D and node voltage as V GS . Figure 16 represents the TM function output curve versus V GS to extract V TSAT for V DS = 0.9 V.

Implementation of TM Process on Test Device
The technique was implemented on the test device. Smooth curves were obtained.
Hence it was easy to extract the threshold values. The V TLIN value and V TSAT value can also be extracted through the TM versus I D curve using the same procedure. On implementation of the mentioned logic, we got the same agreeing values of the threshold voltages.
The outcome of the result was as follows:

Normalized Mutual Integral Difference Method (NMID)
The NMID method was initially developed by He and co-workers in 2002 and it was also stimulated by the integral difference function NMID [31], but in this case normalized by product I D V GS as shown in Equation (9): Consequently, a plot of NMID versus V GS will characterize a maxima at V GS = V TH .  Flat curves of NMID to evaluate NMID max was challenging to extract the analogous threshold values. Figure 18 represents the NMID function output curve versus V GS to extract V TSAT for V DS = 0.9 V.
The outcome of the result was as follows:

Normalized Reciprocal H Function (NRH) Method
The NRH method can also be labelled as "Improved NMID Method". Eliminating the ''1'' term and the factor ''2'' from NMID Equation (11) where I D0 is the drain current at V GS = 0. Limit of the integral can be considered as 0 to V GS in Equation (10). We propose that instead of using H(V GS ) function, its reciprocal NRH(V GS ) should be used to produce narrow maxima or minima: A factor of 2 is added to the denominator in Equation (11) Figure 19 and Figure 20 illustrate the application of this NRH method to the test device for the extraction of V TLIN and V TSAT respectively.

Implementation of NRH Method on Test Device
The technique was implemented on the test device. Smooth curves were obtained.
Flat curves of NRH to evaluate NRH max was challenging to extract the analogous threshold values.
The outcome of the result was as follows:

Reciprocal H Function (RH) Method
In view of TCR, the differential value of I D by itself expressively increases experimental noise, specifically in weak inversion, an analogous function for low gate bias. The plot of dRH/dV GS versus V GS exemplifies the above statement as it can be clearly seen in Figure 21 and Figure 22. The technique was proposed in 2010 based on the integration rather than differentiation to reduce unsolicited signal interference noise [33] [34]: where RH is the reciprocal of function H predefined in NRH method; I D0 is the drain current flow at V GS = 0. Limits of the integral can be considered as 0 to V GS . It is anticipated that the RH function could also be used to extract the threshold voltage. The V TH can be extracted from the maximum negative gradient of the function RH i.e. V GS = V TH analogous to the minimum value of curve dRH/dV GS .

Implementation of RH Method on Test Device
The technique was implemented on the test device. The method was highly affected by the investigational noise. Hence it was challenging to extract the threshold values. As seen in Figure 22 and Figure 23, distinct features like smoothening and filtration of the curve were considered to extract the correct output.
The outcome of the result was as follows:

Self-Extraction Methods
These methods use the self-extracting techniques and circuits to extract the value of threshold voltage. Couple of methods under this category are briefly discussed below. LX142 model accessible in HSPICE, presents the output results as V TH . Therefore, for short channel devices this process appears effectual in extracting V TH and also shows compatibility with the existing transistor models.

HSPICE Command Extraction Method
The HSPICE Command ".OPTION IVTH" was implemented on the test device.
LX142 model accessible in HSPICE, presents the output results as V TH .
The outcome of the result was as follows:  Figure 24.

Automatic Threshold Voltage Extractor Circuit (ATEC) Method
Few other similar ATEC designs with different implementation logics are also proposed to extract the V TH .

Implementation of ATEC Method on Test Device
The technique was implemented on the test device. The bulk driven 10 nm nano-NMOS model was used to simulate the circuit. The test device is made to work in linear region. Hence the outcome will be the threshold voltage in linear region (V TLIN ). The transient analysis of the circuit gave the following results as shown in Figure 25.

Deviation Based Extraction Methods
Under this grouping, the V TH is extracted by determining either the deviation of the value or the difference between the measured values. Couple of methods using this logic are listed in this category and are briefly discussed below [39].

Match-Point (MP) Method
Match-Point method was proposed in 1990 by B. El-Kareh and co-workers. This scheme subjectively evaluates V TH at the value of V GS at which the exponential subthreshold current semi-log extrapolation diverges by 5% from the measured I D .
This MP method exaggerates the weak inversion region neglecting strong inversion.   We propose to calculate V TSAT by plotting D I versus V GS and applying the same 5% deviation logic of Match point method. It was observed that V TLIN value was lower than V TSAT value which is generally unusual.
The outcome of the result was as follows:

Vin-Vout Difference (VVD) Method
In this VVD method, a new interpretation of the threshold voltage is presented as [40]: The method is implemented by performing the transient analysis on the testing device. In other words, it states that V TH can be extracted by the voltage difference between the constant V G and V S at the normalized current in the I D -V S curves. As seen in Figure 28, the circuitry of VVD and the extraction method is straightforward and can be easily applicable in measurement apparatus [27].

Implementation of VVD Method on Test Device
The technique was implemented on the test device. Figure 29 represents the transient Y. Swami, S. Rai  The outcome of the result was as follows: The transient results gave the V out value marginally equal to V in , slightly a bit millivolts lower than V in . Hence, as per the above mentioned logic of the referred extraction method, the calculated V TH is a very small value in millivolts which was not in accord with other extraction method outcomes. The extracted threshold voltage value also seems to be unrealistic. Hence we can accomplish that the VVD extraction method is considerably ineffective at nano-meter technology node.

Hybrid Extraction (HEM) Methods
Under this category, the HEM process uses multiple recognized schemes to extract V TH and combines the advantage of each. One of the hybrid extraction methods is explained below [34].
This Hybrid extraction method overwhelms the constraints of above mentioned extraction techniques and compute V TH for all values of V DS . It syndicates both methods namely CCM and LEM mentioned beforehand to appropriately extract the V TH . Additionally, this method is also unaffected by the arbitrary value of I DCITICAL . For valuation of V TH using this method first the value of V TH for low biased V DS is attained using LEM (see Figure 30). Subsequently, I DCRITICAL is determined using CCM as mentioned above.
Further, for higher value of V DS , V TH is defined as the gate voltage at I D for pre-calculated I DCRITICAL value. However, the extracted value of V TH is not constant as the dependence of g m on other process parameters is not modelled accurately.

Implementation of Hybrid Extraction Method on Test Device
The HEM technique was implemented on the test device. V TLIN was calculated using LEM for I D versus V GS graph with low biased V DS , and correspondingly the I DCRITICAL was also evaluated. Furthermore, I D versus V GS graph is plotted with high biased V DS . Implementing the CCM technique on the plot by using the pre-calculated I DCRITICAL , we are able to calculate V TSAT . Hence we are able to extract V TLIN and V TSAT using Hybrid extraction method as seen in Figure 30.
The outcome of the result was as follows:

Compiled Simulation Results
All the predefined threshold voltage extraction methods were investigated and imple-  The results are tabulated in Table 1. Accuracy can be enhanced by considering more number of measured points.

Application of VTH Extraction Methods to Implement Noise Analysis
Noise analysis of the Resistive load Inverter were performed using various V TH extrac- voltage is equal to input voltage.
Noise margin is the limit of noise that a circuit can endure without compromising the operation of circuit. It assures that logic "1" with finite noise added to it, is still recognized as logic "1" and not logic "0" and vice versa. It is principally the difference between  Figure 32).
• V OH : (Voltage Output High Value). V OH = Vdd because when the input voltage drops below V TH of the inverter, no current flows. No current flow in turn means no voltage drop across the load resistor and V OUT = V dd = V OH . • V OL : (Voltage Output Low Value). If the input is driven to V OL = V dd , then the driver NMOS transistor is "ON" and since (V gs − V t ) > V ds , it is operating in linear mode.
The V OUT will be at V OL and the V IN will be at V OH . • V IH : (Voltage Input High Value). When V IN = V IH , the output is at V OL and the NMOS is in the linear region.
• V IL : (Voltage Input Low Value). To determine noise margin we need V IL which is one of two points where we have unity gain. When input low, output high and NMOS in saturation.

Introduction
Considering the output characteristics of a resistive load inverter; the threshold voltage of the NMOS (V TH ) plays a significant role in determining the shape of the voltage transfer characteristic (V TC ) of a resistive load inverter. The V TH appears as a critical parameter in expressions for V OL , V IL , and V IH . V OH is determined primarily by the power

Noise Margin Analysis of Inverter for Diverse Values of Driver NMOS Threshold (VTH)
Ideally, when input voltage is logic "1", the output voltage is expected to be at logic "0".
Hence, V IH is V dd , and V OL is 0 V as shown in Figure 34. Alternatively, when input voltage is logic "0", output voltage is supposed to be at logic "1". Hence, V IL is 0 V, and V OH is V dd . Using the values, the Noise Margins for an ideal inverter could be defined as follows: • NM L (Noise Margin Low) Practically the situation is not identical. It is observed that due to number of secondary effects like voltage droop, ground bounce, internal resistances, practices, etc.; V OH is slightly less than V dd i.e. dd V′ , whereas V OL is slightly higher that V ss i.e. ss V′ as shown in Figure 33. Hence Noise margins for a practical circuit can be defined as follows: Figure 33. Typical VTC of a resistive load inverter. Figure 34. VTC of an ideal resistive load inverter.
• NM L (Noise Margin Low) Hence, if input voltage (V IN ) lies somewhere between V OL and V IL , it would be detected as logic "0", and would result in an output which is acceptable. Similarly, if input voltage (V IN ) lies between V IH and V OH , it would be detected as logic "1" and would result in an output which is acceptable.

Statistical Inference
Application of the extraction methods were implemented to calculate the Noise Immunity and Noise Margins for Resistive Load Inverter using 10-nm test device with Load Resistance R L = 100 Ω and V dd = 1 V. Referring to Table 2, we can infer number of facts and properties that can be extracted from noise margin analysis regarding various threshold extraction methods.
• We observe that with the increase in the Threshold voltage extraction value, the NM H decreases and NM L increases. For an Ideal Inverter, Noise Margins should be equal. Using QEM method for V TH extraction, we obtain the most optimistic results (NM H ≈ NM L ) in this regards. (Ref. Figure 35 and Figure 36). • Using ".OPTION IVTH" command accessible in SPICE extraction method for V TH extraction, we obtain the maximum output voltage swing i.e. V OH − V OL for resistive load NMOS inverter (Ref. Figure 37). • In the well-designed inverter, the Threshold value of the circuit (V in = V out ) is nearly equal to V dd /2. We obtain the flawless results in this regards using CCM extraction method (Ref. Figure 38).

Conclusion
We presented, reviewed and critically compared several extraction methods currently used to determine the threshold voltage of bulk driven MOSFETs at 10-nm technology node and other various sub 45-nm technology nodes for precise evaluation of the respective method. The relative performance of all the methods was illustrated and compared under similar conditions by applying them to the test devices: bulk driven nano-MOSFETs with 10-nm technology node along with other various sub 45-nm technology nodes. We can perceive that the extracted threshold voltage largely depends on the method used for extraction specifically at nano-scale. The CCM has an ambiguous definition on the critical drain current (I D0 ) contingent on technology being used. The LEM, QEM and TM outcomes are affected by extrinsic resistance effects, mobility degradation, Short Channel Effects and other second order present effects. SD, TD, GM, RH and TCRM are also widely affected by noise and are also not based on ideal threshold voltage definition condition. The MP is seldom used as 5% deviation value gives an ambiguous definition of threshold. The VVD extraction method is considerably ineffective at nano-meter technology node. In NMID and NRH, the correct calculation of maxima in wide ranges makes the extraction task much more difficult. We can also infer number of facts and properties from noise margin analysis performed using various threshold extraction methods. QEM provides the most optimistic balanced noise margin results. The maximum output voltage swing was observed using SPICE extraction method. CCM delivers the most appropriate results in calculating Threshold value of the circuit. The above listed features and properties of various extraction me-thods can be helpful in merging the threshold voltage compact models at nano-level technology nodes.