Circuits and Systems

Vol.7 No.9(2016), Paper ID 69138, 10 pages

DOI:10.4236/cs.2016.79224

 

Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique

 

S. K. Manikandan, C. Palanisamy

 

Department of EEE, Velalar College of Engineering and Technology, Erode, India
Department of Information Technology, Bannari Amman Institute of Technology, Sathyamangalam, India

 

Copyright © 2016 S. K. Manikandan, C. Palanisamy et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article

Manikandan, S. and Palanisamy, C. (2016) Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique. Circuits and Systems, 7, 2593-2602. doi: 10.4236/cs.2016.79224.
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