Circuits and Systems

Vol.8 No.9(2017), Paper ID 79306, 10 pages

DOI:10.4236/cs.2017.89016

 

A Fast FPGA Implementation for Triple DES Encryption Scheme

 

Edni Del Rosal, Sanjeev Kumar

 

IEEE Network Security Research Lab, Department of Electrical/Computer Engineering, The University of Texas Rio Grande Valley, Edinburg, USA
IEEE Network Security Research Lab, Department of Electrical/Computer Engineering, The University of Texas Rio Grande Valley, Edinburg, USA

 

Copyright © 2017 Edni Del Rosal, Sanjeev Kumar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


Rosal, E. and Kumar, S. (2017) A Fast FPGA Implementation for Triple DES Encryption Scheme. Circuits and Systems, 8, 237-246. doi: 10.4236/cs.2017.89016.

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