Circuits and Systems

Vol.8 No.5(2017), Paper ID 76279, 14 pages

DOI:10.4236/cs.2017.85009

 

A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator

 

Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

 

Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan
Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan
Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan
Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan
Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Japan

 

Copyright © 2017 Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


Hida, I. , Takamaeda-Yamazaki, S. , Ikebe, M. , Motomura, M. and Asai, T. (2017) A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator. Circuits and Systems, 8, 134-147. doi: 10.4236/cs.2017.85009.

Copyright © 2020 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.