Circuits and Systems

Vol.4 No.2(2013), Paper ID 29844, 14 pages

DOI:10.4236/cs.2013.42018

 

Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits

 

Abdoul Rjoub, Almotasem Bellah Alajlouni, Hassan Almanasrah

 

Computer Engineering Department, Jordan University of Science and Technology, Irbid, Jordan
Information Technology Department, Balqa’ Applied University, Irbid, Jordan
Computer Engineering Department, Jordan University of Science and Technology, Irbid, Jordan

 

Copyright © 2013 Abdoul Rjoub, Almotasem Bellah Alajlouni, Hassan Almanasrah et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

 

How to Cite this Article


A. Rjoub, A. Alajlouni and H. Almanasrah, "Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits," Circuits and Systems, Vol. 4 No. 2, 2013, pp. 123-136. doi: 10.4236/cs.2013.42018.

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