FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines

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Circuits and Systems

ISSN Print: 2153-1285
ISSN Online: 2153-1293
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E-mail: cs@scirp.org

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"FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines"
written by Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid,
published by Circuits and Systems, Vol.7 No.9, 2016

has been cited by the following article(s):

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[1]	CMOS-compatible Ising and Potts Annealing Using Single Photon Avalanche Diodes
	arXiv preprint arXiv …, 2022

[2]	A highly parameterizable framework for Conditional Restricted Boltzmann Machine based workloads accelerated with FPGAs and OpenCL
	2020

[3]	Integrated analog neurons inspired by mimicking synapses with metal-oxide memristive devices
	2020

[4]	An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity
	2020

[5]	Structural optimisation algorithm of weight correlation analysis for DBN
	2019

[6]	Harnessing Intrinsic Noise in Memristor Hopfield Neural Networks for Combinatorial Optimization
	2019

[7]	The optimization of parallel convolutional RBM based on Spark
	2019

[8]	A shared synapse architecture for efficient FPGA implementation of autoencoders
	PLOS ONE, 2018

[9]	Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays
	2018

[10]	Artificial neuron operations and spike-timing-dependent plasticity using memristive devices for brain-inspired computing
	Japanese Journal of Applied Physics, 2018

[11]	Toward a Hardware-assisted Online Intrusion Detection System Based on Deep Learning Algorithms for Resource-Limited Embedded Systems
	Dissertation, University of Cincinnati, 2018

[12]	情報・神経科学とものづくりの学際融合による人工知能ハードウェア
	2018

[13]	Reducing calculation requirements in FPGA implementation of deep learning algorithms for online anomaly intrusion detection
	2017

[14]	Live Demonstration: Feature extraction system using restricted Boltzmann machines on FPGA
	2017

[15]	Performance Evaluation of DBN Learning on Intel Multi-and Manycore Architectures
	Parallel Processing and Applied Mathematics, 2017

[16]	A Deep Belief Network Based Approach for Bearing Fault Diagnosis
	2016

[1]	CMOS-compatible Ising and Potts annealing using single-photon avalanche diodes Nature Electronics, 2023 DOI:10.1038/s41928-023-01065-0

[2]	A highly parameterizable framework for Conditional Restricted Boltzmann Machine based workloads accelerated with FPGAs and OpenCL Future Generation Computer Systems, 2020 DOI:10.1016/j.future.2019.10.025

[3]	Integrated analog neurons inspired by mimicking synapses with metal-oxide memristive devices Japanese Journal of Applied Physics, 2020 DOI:10.35848/1347-4065/ab8164

[4]	An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2020 DOI:10.1109/A-SSCC48613.2020.9336135

[5]	A shared synapse architecture for efficient FPGA implementation of autoencoders PLOS ONE, 2018 DOI:10.1371/journal.pone.0194049

[6]	Artificial neuron operations and spike-timing-dependent plasticity using memristive devices for brain-inspired computing Japanese Journal of Applied Physics, 2018 DOI:10.7567/JJAP.57.04FK06

[7]	Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018 DOI:10.1109/ISCAS.2018.8351298

[8]	The Optimization of Parallel Convolutional RBM Based on Spark International Journal of Wavelets, Multiresolution and Information Processing, 2018 DOI:10.1142/S0219691319400113

[9]	Hardware Artificial Intelligence Driven by Interdisciplinary Fusion of Information Science, Neuroscience and Manufacturing The Brain & Neural Networks, 2018 DOI:10.3902/jnns.25.148

[10]	Reducing calculation requirements in FPGA implementation of deep learning algorithms for online anomaly intrusion detection 2017 IEEE National Aerospace and Electronics Conference (NAECON), 2017 DOI:10.1109/NAECON.2017.8268745

[11]	Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017 DOI:10.1109/ISCAS.2017.8050402

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