Design and Implementation of Efficient Reversible Arithmetic and Logic Unit

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
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"Design and Implementation of Efficient Reversible Arithmetic and Logic Unit"
written by Subramanian Saravanan, Ila Vennila, Sudha Mohanram,
published by Circuits and Systems, Vol.7 No.6, 2016

has been cited by the following article(s):

[1]	Computer-Aided Developments: Electronics and Communication
	2019

[2]	CERTAIN STUDY ON FABRICATION OF REVERSIBLE QUANTUM DOT PHOTONIC INTEGRATED CIRCUIT
	Caribbean Journal of Science, 2019

[3]	ASIC Design of ALU with different multipliers
	2019

[4]	Computer-Aided Developments: Electronics and Communication: Proceeding of the First Annual Conference on Computer-Aided Developments in …
	2019

[5]	Division circuit using reversible logic gates
	2018

[6]	Speed and area analysis on hierarchy multiplier
	2017

[7]	Design and Implementation of an Efficient Reversible Comparator Using TR Gate
	2016

[8]	Comparative Study and Implementation of Vedic Multiplier for Reversible Logic Based ALU
	2016

[1]	Division circuit using reversible logic gates 2018 International Conference on Advanced Systems and Electric Technologies (IC_ASET), 2018 DOI:10.1109/ASET.2018.8379835

[2]	Speed and area analysis on hierarchy multiplier EPJ Web of Conferences, 2017 DOI:10.1051/epjconf/201716201067

[3]	Design and Implementation of an Efficient Reversible Comparator Using TR Gate Circuits and Systems, 2016 DOI:10.4236/cs.2016.79223

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