A Subthreshold Low-Voltage Low-Phase-Noise CMOS LC-VCO with Resistive Biasing

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ISSN Print: 2153-1285
ISSN Online: 2153-1293
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"A Subthreshold Low-Voltage Low-Phase-Noise CMOS LC-VCO with Resistive Biasing"
written by Jungnam Bae, Saichandrateja Radhapuram, Ikkyun Jo, Takao Kihara, Toshimasa Matsuoka,
published by Circuits and Systems, Vol.6 No.5, 2015

has been cited by the following article(s):

[1]	A 2.2 to 2.9 GHz Complementary Class-C VCO With PMOS Tail-Current Source Feedback Achieving–120 dBc/Hz Phase Noise at 1 MHz Offset
	2019

[2]	Design and Test Issues of a SOl CMOS Voltage Controlled Oscillators for Radiation Tolerant Frequency Synthesizers
	2018

[3]	Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications
	Australian Journal of Electrical and Electronics Engineering, 2018

[4]	A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices
	2016

[5]	A study on performance improvement of RF transmitter IC using genetic algorithm
	Microwave and Optical Technology Letters, 2016

[6]	A low-voltage design of digitally-controlled oscillator based on the gm/ID methodology
	2015

[7]	A Design of 0.7-V 400-MHz Digitally-Controlled Oscillator
	IEICE Transactions on Electronics, 2015

[8]	A low-voltage design of controller-based ADPLL for implantable biomedical devices
	Biomedical Circuits and Systems Conference (BioCAS), 2015 IEEE, 2015

[1]	A 2.2 to 2.9 GHz Complementary Class-C VCO With PMOS Tail-Current Source Feedback Achieving – 120 dBc/Hz Phase Noise at 1 MHz Offset IEEE Access, 2019 DOI:10.1109/ACCESS.2019.2927031

[2]	Design and Test Issues of a SOl CMOS Voltage Controlled Oscillators for Radiation Tolerant Frequency Synthesizers 2018 IEEE East-West Design & Test Symposium (EWDTS), 2018 DOI:10.1109/EWDTS.2018.8524835

[3]	Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications Australian Journal of Electrical and Electronics Engineering, 2018 DOI:10.1080/1448837X.2018.1527101

[4]	A study on performance improvement of RF transmitter IC using genetic algorithm Microwave and Optical Technology Letters, 2016 DOI:10.1002/mop.30180

[5]	A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices IEICE Transactions on Electronics, 2016 DOI:10.1587/transele.E99.C.431

[6]	A study on performance improvement of RF transmitter IC using genetic algorithm Microwave and Optical Technology Letters, 2016 DOI:10.1002/mop.30180

[7]	A low-voltage design of controller-based ADPLL for implantable biomedical devices 2015 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2015 DOI:10.1109/BioCAS.2015.7348405

[8]	A low-voltage design of digitally-controlled oscillator based on the gm/ID methodology 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2015 DOI:10.1109/RFIT.2015.7377929

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