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Reliability of High Speed Ultra Low Voltage Differential CMOS Logic

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DOI: 10.4236/cs.2015.65013    2,722 Downloads   3,121 Views   Citations


In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.

Conflicts of Interest

The authors declare no conflicts of interest.

Cite this paper

Mirmotahari, O. and Berg, Y. (2015) Reliability of High Speed Ultra Low Voltage Differential CMOS Logic. Circuits and Systems, 6, 121-135. doi: 10.4236/cs.2015.65013.


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