Share This Article:

A Very Low Level dc Current Amplifier Using SC Circuit: Effects of Parasitic Capacitances and Duty Ratio on Its Output

Abstract Full-Text HTML XML Download Download as PDF (Size:1259KB) PP. 458-466
DOI: 10.4236/ojapps.2014.49044    2,617 Downloads   2,982 Views  

ABSTRACT

This paper describes a very low level dc current amplifier using switched capacitor (SC) circuit to miniaturize and improve its output response speed, instead of the conventionally used high-oh-mage resistor. A switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier. The simulation results show that the parasitic capacitances that are distributed to the input portion of the amplifier have some effect on offset voltage. From the experimental results, it is seen that the duty ratio of the clock cycle of SC circuit should be in the range from 0.05 to 0.70. It is suggested that the proposed very low level dc current amplifier using SC circuit is an effective way to obtain both a faster output response and its miniaturization.

Conflicts of Interest

The authors declare no conflicts of interest.

Cite this paper

Higa, H. , Onaga, R. and Nakamura, N. (2014) A Very Low Level dc Current Amplifier Using SC Circuit: Effects of Parasitic Capacitances and Duty Ratio on Its Output. Open Journal of Applied Sciences, 4, 458-466. doi: 10.4236/ojapps.2014.49044.

References

[1] Goto, K. and Ishikawa, K. (1979) Design and Construction of High Speed Pico-Ammeter. The Journal of the Vacuum Society of Japan, 22, 235-246. (in Japanese)
http://dx.doi.org/10.3131/jvsj.22.235
[2] Nakamura, I. and Kano, T. (1983) Noise and Fast Response of a Very Small dc Current Amplifier. Oyo Buturi, 52, 330-338. (in Japanese)
[3] Galliana, F. and Capra, P.P. (2010) Hamon 10 × 100 MΩ Resistor Based Traceable Source for Calibration of Picoammeters in the Range 100 pA - 100 nA. Measurement, 43, 1277-1281.
http://dx.doi.org/10.1016/j.measurement.2010.07.006
[4] Galliana, F., Capra, P.P. and Gasparotto, E. (2009) Metrological Management of the High dc Resistance Scale at INRIM. Measurement, 42, 314-321.
http://dx.doi.org/10.1016/j.measurement.2008.07.002
[5] Nakamura, I. and Takemura, M. (1989) Fast Response of a Very Low-Level dc Current Amplifier Using Improvement of Feedback Resistor Shielding Structure. IEICE Transactions on Electronics, J72-C-II, 885-892. (in Japanese)
[6] Nakamura, I. and Kano, T. (1985) High Speed Response of a Very Low Level dc Current Amplifier Using Positive Feedback Loop. Oyo Buturi, 54, 945-951. (in Japanese)
[7] Grebene, A.B. (1984) Bipolar and MOS Analog Integrated Circuit Design. John Wiley & Sons Inc., Hoboken.
[8] Higa, H., Onaga, R., Nakamura, N. and Nakamura, I. (2005) A Basic Study on a Very Low-Level Dc Current Amplifier Using a Switched-Capacitor Circuit: Comparison between Simulation and Experimental Results. Proceeding of the ITC-CSCC2005, Jeju, 3-7 July 2005, 1133-1134.
[9] Weste, N.H.E. and Eshraghian, K. (1999) Principle of CMOS VLSI Design: A Systems Perspective, Maruzen (tr. Tomisawa, T. and Matsuyama, Y.).
[10] Higa, H., Nakamura, N. and Nakamura, I. (2005) A Basic Study on a Very Low-Level dc Current Amplifier Using a Switched-Capacitor Circuit. IEICE Transactions on Fundamentals, E88-A, 1394-1400.

  
comments powered by Disqus

Copyright © 2018 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.