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Buffer Management in the Sliding-Window (SW) Packet Switch for Priority Switching

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DOI: 10.4236/ijcns.2014.77027    2,655 Downloads   3,139 Views   Citations

ABSTRACT

Switch and router architectures employing a shared buffer are known to provide high throughput, low delay, and high memory utilization. Superior performance of a shared-memory switch compared to switches employing other buffer strategies can be achieved by carefully implementing a buffer-management scheme. A buffer-sharing policy should allow all of the output interfaces to have fair and robust access to buffer resources. The sliding-window (SW) packet switch is a novel architecture that uses an array of parallel memory modules that are logically shared by all input and output lines to store and process data packets. The innovative aspects of the SW architecture are the approach to accomplishing parallel operation and the simplicity of the control functions. The implementation of a buffer-management scheme in a SW packet switch is dependent on how the buffer space is organized into output queues. This paper presents an efficient SW buffer-management scheme that regulates the sharing of the buffer space. We compare the proposed scheme with previous work under bursty traffic conditions. Also, we explain how the proposed buffer-management scheme can provide quality-of-service (QoS) to different traffic classes.

Conflicts of Interest

The authors declare no conflicts of interest.

Cite this paper

Munoz, A. and Kumar, S. (2014) Buffer Management in the Sliding-Window (SW) Packet Switch for Priority Switching. International Journal of Communications, Network and System Sciences, 7, 248-255. doi: 10.4236/ijcns.2014.77027.

References

[1] Kumar, S. (2003) The Sliding-Window Packet Switch: A New Class of Packet Switch Architecture with Plural Memory Modules and Decentralized Control. IEEE Journal on Selected Areas in Communications, 21, 656-673. http://dx.doi.org/10.1109/JSAC.2003.810513
[2] Choudhury, A.K. and Hahne, E.L. (1998) Dynamic Queue Length Thresholds for Shared-Memory Packet Switches. IEEE/ACM Transactions of Networking, 6, 130-140.
http://dx.doi.org/10.1109/90.664262
[3] Kumar, S., Munoz, A. and Doganer, T. (2004) Performance Comparison of Memory-Sharing Schemes for Internet Switching Architecture. Proceedings of the International Conference on Networking.
[4] Kamoun, F. and Kleinrock, L. (1980) Analysis of Shared Finite Storage in a Computer Network Node Environment under General Traffic Conditions. IEEE Transactions Communications, 28, 992-1003. http://dx.doi.org/10.1109/TCOM.1980.1094756
[5] Arpaci, M. and Copeland, J.A. (2000) Buffer Management for Shared-Memory ATM Switches. IEEE Communications Surveys & Tutorials, 3, 2-10. http://dx.doi.org/10.1109/COMST.2000.5340716
[6] Thareja, A.K. and Agarwala, A.K. (1984) On the Design of Optimal Policy for Sharing Finite Buffers. IEEE Transactions Communications, 32, 737-740. http://dx.doi.org/10.1109/TCOM.1984.1096120
[7] Munoz, A. and Cantrell, C.D. (2009) Memory-Configuration and Memory-Bandwidth in the Sliding-Window (SW) Switch Architecture. 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, 2-5 August 2009, 288-291.
[8] Yamanaka, K., et al. (1997) Scalable Shared-Buffering ATM Switch with a Versatile Searchable Queue. IEEE Journal on Selected Areas in Communications, 15, 773-784.
http://dx.doi.org/10.1109/49.594840
[9] Kumar, S. and Munoz, A. (2005) Performance Comparison of Switch Architectures with Parallel Memory Modules. IEEE Communications Letters, 9, 1015-1017.
http://dx.doi.org/10.1109/LCOMM.2005.11021

  
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