Share This Article:

Analogue and Mixed-Signal Production Test Speed-Up by Means of Fault List Compression

Abstract Full-Text HTML Download Download as PDF (Size:815KB) PP. 407-421
DOI: 10.4236/cs.2013.45054    4,536 Downloads   6,270 Views   Citations


Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. The purpose of this paper is to propose a novel fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. Criteria to partition the fault list in strata, and to identify representative faults are presented and discussed. A fault representativeness metric is proposed, based on an error probability. The proposed methodology allows different tradeoffs between fault list compression and fault representation accuracy. These tradeoffs may be optimized for each test preparation phase. The fault representativeness vs. fault list compression tradeoff is evaluated with an industrial case study—a DC-DC (switched buck converter). Although the methodology is presented in this paper using a very simple fault model, it may be easily extended to be used with more elaborate fault models. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.

Conflicts of Interest

The authors declare no conflicts of interest.

Cite this paper

N. Guerreiro, M. Santos and P. Teixeira, "Analogue and Mixed-Signal Production Test Speed-Up by Means of Fault List Compression," Circuits and Systems, Vol. 4 No. 5, 2013, pp. 407-421. doi: 10.4236/cs.2013.45054.


[1] J. Parky, S. Madhavapeddiz, A. Paglieri, C. Barrz and J. Abraham, “Defect-Based Analog Fault Coverage Analysis Using Mixed-Mode Fault Simulation,” IEEE 15th International of Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 09, Scottsdale, 10-12 June 2009, pp. 1-6.
[2] R. Wilson, “Under the Lid: Analog Test Is Suddenly the Critical Ingredient,” EDN, 7 January 2010.
[3] T. Golonek, D. Grzechca and J. Rutkowski, “Analog Ic Fault Diagnosis by Means of Supply Current Monitoring in Test Points Selected Evolutionarily,” International Conference on Signals and Electronic Systems (ICSES), Gliwice, 7-10 September 2010, pp. 397-400.
[4] S. Sindia, V. Singh and V. Agrawal, “Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients,” 23rd International Conference on VLSI Design, Bangalore, 3-7 January 2010, pp. 288-293.
[5] A. Madian, H. Amer and A. Eldesouky, “Catastrophic Short and Open Fault Detection in Mos Current Mode Circuits: A Case Study,” 12th Electronics Conference on Biennial Baltic (BEC), Tallinn, 4-6 October 2010, pp. 145-148.
[6] S. Spinks, C. Chalk, I. Bell and M. Zwolinski, “Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations,” Proceedings of 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, 20-22 October 1997, pp. 100108.
[7] “International Technology Roadmap for Semiconductors,” 2009.
[8] A. Bounceur, S. Mir and E. Simeu, “Cat Platform for Analogue and Mixed-Signal Test Evaluation and Optimization,” International Conference in Very Large Scale Integration, Nice, 16-18 October 2006, pp. 320-325. doi:10.1109/VLSISOC.2006.313254
[9] F. Lui and S. Ozev, “Statistical Test Development for Analog Circuits under High Process Variations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 8, 2007, pp. 14651477.
[10] E. Yilmaz and S. Ozev, “Test Application for Analog/rf Circuits with Low Computational Burden,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 6, 2012, pp. 968-979.
[11] L. Fang, Y. Zhong, H. van Donk and Y. Xing, “Implementation of Defect Oriented Testing and ICCQ Testing for Industrial Mixed-Signal IC,” 16th Asian Test Symposium, Biejing, 8-11 October 2007, pp. 404-412. doi:10.1109/ATS.2007.93
[12] B. Kruseman, B. Tasic, C. Hora, J. Dohmen, H. Hashempour, M. van Beurden and Y. Xing, “Defect Oriented Testing for Analog/Mixed-Signal Designs,” IEEE Design & Test of Computers, Vol. 29, No. 5, 2012, pp. 72-80. doi:10.1109/MDT.2012.2210852
[13] N. Guerreiro and M. Santos, “Mixed-Signal Fault Equivalence: Search and Evaluation,” 20th Asian Test Symposium (ATS), New Delhi, 20-23 November 2011, pp. 377382.
[14] M. L. Bushnell and V. D. Agrawal, “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits,” Kluwer Academic Publishers, city, 2002.
[15] N. Guerreiro, M. Santos and P. Teixeira, “Fault List Compression for Cost-Effective Analogue and Mixed-Signal Fault Simulation,” 27thConference on Design of Circuits and Integrated Systems, Avignon, 28-30 November 2012, pp. 261-266.
[16] A. Bounceur, S. Mir and E. Simeu, “Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing,” Journal of Electronic Testing, Vol. 23, No. 6, 2007, pp. 471-484. doi:10.1007/s10836-007-5006-6

comments powered by Disqus

Copyright © 2018 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.