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Performance of Double-Pole Four-Throw Double-Gate RF CMOS Switch in 45-nm Technology

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DOI: 10.4236/wet.2010.12008    5,362 Downloads   10,656 Views   Citations

ABSTRACT

In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semicon- ductor (DP4T DG RF CMOS) switch for operating at the 1 GHz is implemented with 45-nm CMOS process technology. This proposed RF switch is capable to select the data streams from the two antennas for both the transmitting and receiving processes. For the development of this DP4T DG RF CMOS switch we have explored the basic concept of the proposed switch circuit elements required for the radio frequency systems such as drain current, threshold voltage, resonant frequency, return loss, transmission loss, VSWR, resistances, capacitances, and switching speed.

Conflicts of Interest

The authors declare no conflicts of interest.

Cite this paper

V. Srivastava, "Performance of Double-Pole Four-Throw Double-Gate RF CMOS Switch in 45-nm Technology," Wireless Engineering and Technology, Vol. 1 No. 2, 2010, pp. 47-54. doi: 10.4236/wet.2010.12008.

References

[1] Skyworks Solutions Inc., “Application Note, APN1002, Design with PIN Diodes,” Woburn, July 2005.
[2] J. Park and Z. Q. Ma, “A 15 GHz CMOS RF Switch Employing Large Signal Impedance Matching,” Proceeding of Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, San Diego, 2006, pp. 1-4.
[3] V. M. Srivastava, K. S. Yadav and G. Singh, “Application of VEE Pro Software for Measurement of MOS Device Parameter Using C-V Curve,” International Journal of Computer Applications, Vol. 1, No. 7, March 2010, pp. 43-46.
[4] V. M. Srivastava, “Capacitance-Voltage Measurement for Characterization of a Metal Gate MOS Process,” International Journal of Recent Trends in Engineering, Vol. 1, No. 4, May 2009, pp. 4-7.
[5] L. E. Microelectron and A. B. Stockholm, “Overlooked Interfacial Silicide-Polysilicon Gate Resistance in MOS Transistors,” IEEE Transactions on Electron Devices, Vol. 48, No. 9, September 2001, pp. 2179-2181.
[6] J. P. Carmo, P. M. Mendes, C. Couto and J. H. Correia “A 2.4-GHz RF CMOS Transceiver for Wireless Sensor Applications,” Proceeding of International Conference on Electrical Engineering, Coimbra, 2005, pp. 902-905.
[7] P. Mekanand and D. Eungdamorang, “DP4T CMOS Switch in a Transceiver of MIMO System,” Proceeding of 11th IEEE International Conference of Advanced Communication Technology, Korea, 2009, pp. 472-474.
[8] P. H. Woerlee, et al, “RF CMOS performance trends,” IEEE Transaction on Electron Devices, Vol. 48, No. 8, August 2001, pp. 1776-1782.
[9] W. L. Chan et al, “A 60 GHz-Band 1 V, 11.5 dBm Power Amplifier with 11% PAE in 65-nm CMOS,” International Solid State Circuits Conference, San Francisco, 2009, pp. 380-381.
[10] A. Valdes-Garcia, et al, “60 GHz Transmitter Circuits in 65-nm CMOS,” Radio Frequency Integrated Circuits Symposium, 2008, Atlanta, pp. 641-644.
[11] Y. Cheng and M. Matloubian, “Frequency Dependent Resistive and Capacitive Components in RF MOSFETs,” IEEE Electron Device Letters, Vol. 22, No. 7, July 2001, pp. 333-335.
[12] T. H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits,” 2nd Edition, Cambrige Univrsity Press, New York, 2004.
[13] R. H. Caverly, S. Smith and J. G. Hu, “RF CMOS Cells for Wireless Applications,” Journal of Analog Integrated Circuits and Signal Processing, Vol. 25, No. 1, 2001, pp. 5-15.
[14] V. M. Srivastava, K. S. Yadav and G. Singh, “Double Pole Four Throw Switch Design with CMOS Inverter,” Proceeding of 5th IEEE International Conference on Wireless Communication and Sensor Network, 15-19 December 2009, pp. 1-4.
[15] U. Gogineni, J. Alamo and C. Putnam, “RF Power Potential of 45 nm CMOS Technology,” Proceeding of Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, New Orleans, 2010, pp. 204-207.
[16] T. Manku, “Microwave CMOS Device Physics and Design,” IEEE Journal of Solid State Circuits, Vol. 34, No. 3, March 1999, pp. 277-285.
[17] S. H. Lee, C. S. Kim and H. K. Yu, “A Small Signal RF Model and its Parameter Extraction for Substrate Effects in RF MOSFETs,” IEEE Transaction on Electron Devices, Vol. 48, No. 7, July 2001, pp. 1374-1379.
[18] S. Kang and Y. Leblebici, “CMOS Digital Integrated Circuits Analysis and Design,” 3rd Edition, 2002, McGraw-Hill, New York, NY, USA.
[19] R. Baker, H. Li and D. Boyce, “CMOS Circuit Design, Layout, and Simulation” 3rd Edition, IEEE Press Series on Microelectronic Systems, 2010.
[20] U. Gogineni, et al, “Effect of Substrate Contact Shape and Placement on RF Characteristics of 45-nm Low-Power CMOS Devices,” IEEE Radio Frequency Integrated Circuits Symposium, Massachusetts, 2009, pp. 163-166.
[21] F. J. Huang, “A 0.5-μm CMOS T/R Switch For 900 MHz Wireless Applications,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 3, 2001, pp. 486-492.
[22] C. Ta, E. Skafidas and R. Evans, “A 60-GHz CMOS Transmit/Receive Switch,” IEEE Radio Frequency Integrated Circuits Symposium, Hawaii, 2007, pp. 725-728.
[23] V. M. Srivastava, K. S. Yadav and G. Singh, “Mea- surement of Oxide Thickness for MOS Devices, Using Simulation of SUPREM Simulator,” International Journal of Computer Applications, Vol. 1, No. 6, March 2010, pp. 66-70.
[24] Y. Cheng and M. Matloubian, “Parameter Extraction of Accurate and Scalable Substrate Resistance Components in RF MOSFETs,” IEEE Electron Device Letters, Vol. 23, No. 4, April 2002, pp. 221-223.
[25] V. M. Srivastava, “Relevance of VEE Programming for Measurement of MOS Device Parameters,” Proceedings of IEEE International Advance Computing Conference, Patiala, March 2009, pp. 205-209.
[26] S. M. Sze, “Semiconductor Devices: Physics and Technology,” 2nd Edition, Tata McGraw Hill, New Delhi, 2004.
[27] V. M. Srivastava, K. S. Yadav and G. Singh, “Designing Parameters for RF CMOS Cells,” International Journal of Circuits and Systems, Vol. 1, No. 2, October 2010.
[28] V. M. Srivastava, K. S. Yadav and G. Singh, “Analysis of Attenuation, Isolation and Switching Speed of DP4T Double Gate RF CMOS Switch Design,” Proceeding of IEEE International Conference on Industrial Electronics, Control & Robotics, NIT Rourkela, India, 27-29 December 2010.

  
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