A Storage Architecture for High Speed Signal Processing: Embedding RAID 0 on FPGA

Ningxiao Sun, Qiongzhi Wu, Zhaojian Jin

Beijing Institute of Technology.

DOI: 10.4236/jsip.2012.33050                

Abstract

The article proposes a new architecture based on RAID 0 tech in computer science for signal processing field to store high speed data. It is composed of SSD driven by FPGA, called SSD-based RAID on FPGA. This new architecture features high storage rate, mass capacity and small volume, and it is an efficient solution to store high speed data. The article describes the construction of SRF in details, and shows the test result of a demo system based on the architecture.

Keywords

RAID on FPGA; SSD; High Speed Data Storage

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	K. Park, “Reliability and Performance Enhancement Technique for SSD Array Storage System Using RAID Mechanism,” The 9th International Symposium on Communications and Information Technology (ISCIT 2009), 28-30 September 2009, pp. 140-145.
[2]	W. F. Jones, “A Digital Architecture for Routinely Storing and Buffering the Entire 64-Bit Event Acquisition in Clinical Real-Time 3-D PET: Embedding a 400 Mbyte/ sec SATA RAID 0 Using a Set of Four Solid- Solid-State Drives,” 2008 IEEE Nuclear Science Symposium Conference, 19-25 October 2008, pp. 5036-5040. doi:10.1109/NSSMIC.2008.4774371
[3]	J. Ren, “I-CASH: Intelligently Coupled Array of SSD and HDD,” The 17th International Symposium on High Performance Computer Architecture (HPCA), 12-16 February 2011, pp. 278-289.
[4]	W. Wu, “Implementing a Serial ATA Controller base on FPGA,” Computational Intelligence and Design (ISCID 09), Vol. 1, 12-14 December 2009, pp. 467-470.
[5]	S. S. Rizvi, “Data Storage Framework on Flash Memory Based SSD RAID 0 for Performance Oriented Applications,” The 2nd International Conference on Computer and Automation Engineering (ICCAE), Vol. 1, 26-28 February 2010, pp. 126-128.
[6]	K. R. Dandekar, H. Ling and G. H. Xu, “Smart Antenna Array Calibration Procedure including Amplitude and Phase Mismatch and Mutual Coupling Effects,” IEEE Conference on Personal Wireless Communications (PWC), Vol. 12, 2000, pp. 293-297.
[7]	Serial ATA Working Group, “Serial ATA High Speed Serialized AT Attachment Rev 1.0a,” Serial ATA Working Group, 2002, pp. 117-123.