A modular and generic monolithic integrated MEMS process for integrating CMOS technology with polysilicon microstructures is presented. The proposed process flow is designed with an intra CMOS approach to fabricate the microstructures into trenches without the need of planarization techniques. After annealing at 1000°C at significant period of time, it is shown that Id- Vg characteristics of the CMOS transistors remain almost unchanged, indicating their robustness to the intra process fabrication for the micromechanical structures. The CMOS module is designed with a 3 μm length as a minimum feature and this process results with a minimum of residual strain and stress on the micromechanical devices ( ε = 1.28 × 10 -4 and σ = -21 MPa).
The MEMS (Micro-Electro-Mechanical Systems) acronym brings to mind mechanical structures of micrometric dimensions performing an electronically controlled preset function [
A generic integrated circuit process fabrication is one that can fabricate more than a single device. The CMOS technology proposed in this work is a generic one. However, specific microcomponents technology usually results quite limited by some specific applications. The goal of our MEMS technology is to develop a generic and modular process capable of integrating intelligent and varied microstructures by exploiting the fabrication sequence described in this work. Considering Pre-, Intra- and Post-CMOS, these approaches have in common that the production of the MEMS is adapted to the well developed CMOS processes. This means that the CMOS process could modify the original sequence of fabrication process in order to produce a new MEMS fabrication process. Hence, in this work critical thermal fabrication steps are discussed about the compatibility of CMOS with the microcomponents modules for the development of a generic MEMS technology.
The integration of a new MEMS technology is required for the design and development of systems satisfying the need of more and accurate functionality at lower cost. In this way we propose a MEMS technology for thermomechanical applications that may be developed by stages, the starting point is the development of a set of force-sensing circuits mainly composed by suspended Wheatstone bridges and chevron actuators. A long-term objective will be considering the development of a multi-purpose MEMS technology, which considers other related microcomponents. The monolithic integration approach will be developed considering a Polysilicon surface micromachining module and a CMOS module, whose integration is designed considering (0 0 1), 6-inch diameter, silicon wafers.
The surface micromachining module was already developed, and uses polysilicon (Poly) films as structural materials. Such module offers two structural levels, phospho-silicate glass (PSG) films as sacrifice material, and aluminum films for interconnections [
The CMOS module is under development; with the purpose of fabricate digital circuits with 3μm-length as minimum feature and ±5 supply voltage. For matching the threshold voltage transistors, a twin-well diffusion and latch up-free structure were designed [
Using the PolyMEMS INAOE technology®, several static and dynamic microcomponents have been fabricated [
Then, a systematic analysis about the residual stress on the 2.0 μm-thick Poly films is performed. Poly films were doped during 70 minutes at 1000˚C [
According to the thermal load for the poly films, we took the Young modulus E = 154 GPa [
In
The CMOS module consists of 9 mask and 12 lithography steps. The main blocks are briefly discussed in the following: 10 - 20 Ω-cm (~5 × 1014 cm−3), p-type, 6-inch diameter, (0 0 1) silicon wafers are selected as the substrate. Initially the formation of the N- and P- wells, as twin wells, are ion implanted and the drive-in thermal diffusion is performed at 1200˚C. The junction depth (3.5 μm) is designed to be deep enough to avoid vertical punch-trough. The active areas are defined by using Poly buffered local oxidation of silicon (PBLOCOS) for a precise feature definition. A p-channel stopper is used to reduce the spacing between devices and providing better isolation. A 200Å gate oxide is thermally grown at 900˚C in dry oxidation. 400 nm of Poly films are low-pressure chemically vapor-deposited (LPCVD) at 650˚C, after that a 1000˚C phosphorus doping is performed during 30 minutes. This process is designed with shallow source/drain junctions (0.7 μm) as well as low gate and drain/source sheet resistances to minimize the delay and increase the current drive of the devices. The titanium silicide (TiSi2) electrodes are defined using a self-aligned process realized at 900˚C in nitrogen ambient. A precise low-dose of boron ions is implanted for threshold adjusting of CMOS transistors. Interconnecting aluminum film is deposited and patterned, and finally a 450˚C sintering is performed. The main process specifications are summarized in
Parameter | Symbol | Value | Units |
---|---|---|---|
Threshold Voltage N/P channels | Vto | 700 | mV |
Gate Oxide Thickness | Tox | 20 | nm |
N-Well Depth | Xnwell | ~3.5 | μm |
N-Well Surface Concentration | Nnwell | ~4.5 × 1015 | cm−3 |
P-Well Depth | Xpwell | ~3.5 | μm |
P-Well Surface Concentration | Npwell | ~9 × 1016 | cm−3 |
Poly Gate thickness | Tg | 0.4 | μm |
Source/Drain Junction Depth | Xj | 0.7 | μm |
Some materials and chemical ambient for full fabrication must be correlated with some type of integration approach. A Post-CMOS approach using the current PolyMEMS INAOE module cannot be compatible due to the requirements for the LPCVD Poly films, which are doped and thermally annealed at 1000˚C for a time longer than 30 minutes. The other options could be the Pre and Intra-CMOS approaches. In this sense, the PolyMEMS INAOE® technology has a thermal budget limited to 1000˚C, and according to the CMOS thermal budget shown in
For developing a practical intra-CMOS process, it is necessary to consider that the CMOS module is more sensitive to thermal treatments than the polysilicon microstructures. Because the goal is the integration of these different fabrication modules, a thermal study related with dopant profiles is required. For the analytical study, considering the varied CMOS doping steps and the related annealing cycles, a wide range of overall annealing time must be considered. The simulation routines were performed using SILVACO® suite that contains the Athena and Atlas environments in which the tuning of all the modules was performed with the data obtained from the characterization of the 3μm CMOS technology here developed.
For example, the final part of the CMOS module is designed with a silicon/silicide interface for electrical interconnection, which imposes limitations to the post thermal cycles to a 900˚C maximum range, for avoiding structural interface damages due to titanium silicide (TiSi2) reactivity [
As an example of our design approach, a thermal simulation was performed to demonstrate the invariance of the P/N wells (CMOS) after a long annealing time at 1000˚C as that required for the microstructure fabrication.
at 1000˚C, could really be considered. The most significant issue observed after the very long post-annealing treatments, was a slight surface concentration variation at both wells, which is due to boron and phosphorus segregation at both wells/capping oxide interfaces [
The way for the electronic-mechanical coupling is another key step in the design of the integrated process.
The M3EMS (Modular Monolithic MEMS) technology developed at Sandia National Laboratories was one of the first demonstrations of the MEMS-first integration concept [
In our approach, we are considering the case when the microstructures are placed inside a shallow trench. In a general trace
Considering general aspects for a trench some morphology requirements must be carefully considered. For example in the integration work presented in [
In our approach without planarization step, the presence of material stacking around the trench, similar to
The proposed monolithic integrated MEMS fabrication process is divided into four main sections; all the fabrication sequence is completed with 13 masks and 16 photolithography steps:
1) CMOS Part I. The process starts with an initial thin oxide (~200Å) to define the alignment marks and then the trenches are defined by using aqueous TMAH solution for CMOS compatibility. Low dose ion implantation for P and N wells and immediately a thermal drive-in at 1200˚C is performed in nitrogen ambient during 200 minutes. These steps are listed below.
2) Poly Microstructures. An insulator film is deposited for electrical isolation between the microstructures and the surface wafer. Then a sacrificial material is deposited followed by the deposition, doping and patterning of the structural material inside the trenches. A thermal treatment is realized at 1000°C to minimize the residual stress.
3) CMOS Part II. After the complete definition of the microstructures, the CMOS process sequence is realized in the top surface of the wafer. The standard PBLOCOS CMOS process is realized and the microstructures remain covered by the stacked materials from the local oxidation process. Field oxidation has a thermal cycle of 1000˚C for 2 hours, and serves as a stress reduction thermal cycle for the microstructures. The following fabrication sequence is listed below.
4) Interconnections and Releasing. The passivation layer is deposited to protect both the CMOS and microstructures devices. The interconnection between the CMOS and the microstructures is carried out in the metallization step by using a sputtered aluminum film to ensure proper step coverage from the top of the wafer (CMOS area) to the bottom of the trench (microstructure area). The final step in the fabrication process is the sacrificial etch to release the microstructures. The last etching process depends on the specific microstructure geometries, and it can be done by some dry or wet etching technique.
discrete transistors and after 2000 minutes of annealing time. The slight variations for the drain current Id are corresponding with the graphs shown in
A generic and modular design approach for a monolithic MEMS process is proposed without the need of any planarization techniques. The integration is realized with CMOS devices and polysilicon microstructures. From the simulation results, it can be concluded that a non-significant degradation on the CMOS performance devices is observed after MEMS fabrication. The intra process approach showed in this case, to be the best approach for a modular design of a MEMS fabrication process. The thermal budget of the modules plays a crucial role, because it sets the conditions for obtaining the complete set of devices fabricated near their optimal point, that is, without degradation of current handling and without Vto shift in the CMOS process and with the minimum residual stress on the micromechanical devices.
This work was supported by CONACyT-México under granting the scholarship 329012. Authors also acknowledge the technical support of Ignacio Juarez, Mauro Landa, and Oscar Aponte from INAOE.
Carlos Ramón Báez Álvarez,Álvarez, Mónico Linares Aranda,Alfonso Torres Jácome,Mario Moreno Moreno,Joel Molina Reyes,Carlos Zúñiga Islas,Wilfrido Calleja Arriaga, (2016) A Generic MEMS Fabrication Process Based on a Thermal Budget Approach. Journal of Electronics Cooling and Thermal Control,06,97-107. doi: 10.4236/jectc.2016.62009