Berg, Y. and Mirmotahari, O. (2012) Ultra Low-Voltage and High Speed Dynamic and Static Cmos Precharge Logic. FTFC 2012: The 11th International Conference of Faible Tension Faible Consommation (FTFC), IARIA, Paris, 6-8 June 2012, 1-4.
http://dx.doi.org/10.1109/ftfc.2012.6231718

has been cited by the following article:

• TITLE: NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates

  AUTHORS: Ali Dadashi, Omid Mirmotahari, Yngvar Berg

  KEYWORDS: Ultra Low Voltage (ULV), Semi-Floating-Gate (SFG), Speed, NOR Gate, Monte Carlo, TSMC 90 nm, CMOS

  JOURNAL NAME: Circuits and Systems, Vol.7 No.8, June 27, 2016

  ABSTRACT: In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.