TITLE:
Discharge Characteristics of a Triple-Well Diode-String ESD Clamp
AUTHORS:
Jin Young Choi
KEYWORDS:
ESD Protection, Diode String, Triple Well, Device Simulation, CMOS, RF IC
JOURNAL NAME:
Circuits and Systems,
Vol.9 No.5,
May
31,
2018
ABSTRACT: In this work, DC and transient characteristics of a 4 diode string utilizing triple-well technologies as a VDD-VSS clamp device for ESD protection are analyzed in detail based on 2-dimensional device and mixed-mode simulations. It is shown that there exists parasitic pnp bipolar transistor action in this device leading to a sudden increase in DC substrate leakage if anode bias is getting high. Through transient simulations for a 2000 V PS-mode HBM ESD discharge event, it is shown that the dominant discharge path is the one formed by a parasitic pnpn thyristor and a parasitic npn bipolar transistor in series. Percentage ratios of the various current components regarding the anode current at its current peaking are provided. The mechanisms involved in ESD discharge inside the diode-string clamp utilizing triple-well technologies are explained in detail, which has never been done anywhere in the literature based on simulations or measurements.