TITLE:
Design and Analysing the Various Parameters of CMOS Circuit’s under Bi-Triggering Method Using Cadence Tools
AUTHORS:
A. Sridevi, V. Lakshmiprabha, N. Prabhu
KEYWORDS:
Bi-Triggering, Power Analysis, Energy Analysis, Circuit Simulation, Delay Analysis, Sub Clock Method
JOURNAL NAME:
Circuits and Systems,
Vol.7 No.9,
July
28,
2016
ABSTRACT: Reducing the power and
energy required by the device/circuit to operate is the main aim of this paper.
Here the new design is implemented to reduce the power consumption of the
device using the triggering pulses. The proposed triggering method uses a
complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground
leakage suppressor (i.e.); these designs are named as Trig01 and Trig10
designs. In Trig01 design the pair of CMOS is placed in the voltage divider
part; similarly in Trig10 design the pair of CMOS is placed at the ground
leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc.
are designed with these technologies and these gates are designed with 180 nm
technology file in the cadence tool suite; compared to the normal CMOS gates,
the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used
as Bi-Trig control signaling inputs. There are 2 control inputs and thus 22= 4 combination of controlling is done
(i.e.); both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON
and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit,
the mode of operation is switched to any one of the combination. If the output
of the circuit is not used anywhere in the total block, that specified circuit
can be switched into idle mode by means of switched OFF both the pMOS and nMOS
transistor in the control unit. This reduces the leakage current and also the
power wastage of the circuits in the total block. Bi-Trig controlled circuit
reduces the power consumption and leakage power of the circuit without
affecting a performance of the circuits.