TITLE:
Implementation of N-Bit Binary Multiplication Using N - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method
AUTHORS:
M. Nisha Angeline, S. Valarmathy
KEYWORDS:
Nikhilam Sutra, Numerical Strength Reduction, Karatsuba, Vedic Multiplier, Weight Reduction
JOURNAL NAME:
Circuits and Systems,
Vol.7 No.9,
July
19,
2016
ABSTRACT: This paper is designed to
introduce new hybrid Vedic algorithm to increase the speed of the multiplier.
This work combines the principles of Nikhilam sutra and Karatsuba algorithm.
Vedic Mathematics is the mathematical system to solve the complex computations
in an easier manner. There are specific sutras to perform multiplication.
Nikhilam sutra is one of the sutra. But this has some limitations. To overcome
the limitations, this sutra is combined with Karatsuba algorithm. High speed
devices are required for high speed applications with compact size. Normally
multipliers require more power for its computation. In this paper, new
multiplication algorithm for the multiplication of binary numbers is proposed
based on Vedic Mathematics. The novel portion in the algorithm is found to be
in the calculation of remainder using complement method. The size of the
remainder is always set as N - 1 bit for any combination of input.
The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by (N - 1) bit multiplication. Numerical
strength reduction is done through Karatsuba algorithm. The results show that
the reduction in hardware leads to reduction in the delay.