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Dick, R. (2013) E3S Benchmark.
http://ziyang.eecs.umich.edu/~dickrp/e3s/

has been cited by the following article:

  • TITLE: Design of Efficient Router with Low Power and Low Latency for Network on Chip

    AUTHORS: M. Deivakani, D. Shanthi

    KEYWORDS: Network on Chip, Router, Processing Element, Wireless Link, Power Consumption, Average Packet Latency

    JOURNAL NAME: Circuits and Systems, Vol.7 No.4, April 27, 2016

    ABSTRACT: The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.