[1]
|
H. Mahmoodi-Meimand and K. Roy, “A Leakage-Toler ant High Fan-in Dynamic Circuit Style,” IEEE Interna tional Systems-on-Chip Conference, 17-20 September 2003, pp. 117-120. doi:10.1109/SOC.2003.1241475
|
[2]
|
J.-S. Wang, S.-J. Shieh, C. Yeh and Y.-H. Yeh, “Pseudo Footless CMOS Domino Logic Circuits for High-Per formance VLSI Designs,” IEEE International Symposium on Circuits and Systems, Hiroshima, 25-28 July 2004, pp. 401-404.
|
[3]
|
V. Kursun and E. G. Friedman, “Domino Logic with Va riable Threshold Voltage Keeper,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 6, 2003, pp. 1080-1093.
|
[4]
|
Y. Taur and T. H. Hing, “Fundamentals of Modern VLSI Devices,” Cambridge University Press, New York, 1998, pp. 120-128.
|
[5]
|
K. Roy, et al., “Leakage Current Mechanisms and Leak age Reduction Techniques in Deep-Submicrometer CMOS Circuits,” IEEE Proceedings, Vol. 91, No. 2, 2003, pp. 306-327. doi:10.1109/JPROC.2002.808156
|
[6]
|
Y. Taur and T. H. Hing, “Fundamentals of Modern VLSI Devices,” Cambridge University Press, New York, 1998, pp. 94-95.
|
[7]
|
Y. Taur and T. H. Hing, “Fundamentals of Modern VLSI Devices,” Cambridge University Press, New York, 1998, pp. 97-99.
|
[8]
|
K. Roy and S. C. Prasad, “Low-Power CMOS VLSI Circuit Design,” Wiley Interscience Publications, New York, 2000, pp. 28-29.
|
[9]
|
K. Roy and S. C. Prasad, “Low-Power CMOS VLSI Circuit Design,” Wiley Interscience Publications, New York, 2000, pp. 27-28.
|
[10]
|
Z. Liu and V. Kursun, “Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies,” Transactions on Circuits and Systems Part II—Express Briefs, Vol. 53, No. 8, 2006, pp. 692-696.
|
[11]
|
H. Sasaki, M. Ono, T. Ohguro, S. Nakamura, M. Satio and Iwai, “1.5 nm Direct-Tuneling Gate Oxide Si MOS FETs,” IEEE Transactions on Electron Devices, Vol. 43, No. 8, 1996, pp. 1233-1242.
|
[12]
|
F. Moradi and A. Peiravi, “An Improved Noise—Tolerant Domino Logic Circuit for High Fan-In Gates,” IEEE Pro ceedings, 2005, pp. 116-121.
|
[13]
|
M. C. Johnson, D. Somasekhar, L. Y. Chiou and K. Roy, “Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 10, No. 1, 2002, pp. 1-5. doi:10.1109/92.988724
|
[14]
|
S. Narendra, S. Borkar, V. De, D. Antoniadis and A. P. Chandrakasan, “Scaling of Stack Effect and Its Application for Leakage Reduction,” IEEE International Symposium on Low Power Electronics and Design, August 2001, pp. 195-200.
|
[15]
|
S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda and D. Blaauw, “Duet: An Accurate Leakage Estimation and Op timization Tool for Dual-Vt Circuits,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 10, No. 2, 2002, pp. 79-90. doi:10.1109/92.994980
|