Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions ()
ABSTRACT
An open
source high level synthesis fixed-to-floating and floating-to-fixed conversion tool
is presented for embedded design, communication systems, and signal processing
applications. Many systems use a fixed point number system. Fixed point numbers
often need to be converted to floating point numbers for higher accuracy,
dynamic range, fixed-length transmission limitations or end user requirements.
A similar conversion system is needed to convert floating point numbers to
fixed point numbers due to the advantages that fixed point numbers offer when compared with floating point number
systems, such as compact hardware, reduced verification time and design effort. The latest
embedded and SoC designs use both number systems together to improve accuracy
or reduce required hardware in the same design. The proposed open source design
and verification tool converts fixed point numbers to floating point numbers,
and floating point numbers to fixed point numbers using the IEEE-754 floating
point number standard. This open source design tool generates HDL code and its
test bench that can be implemented in FPGA and VLSI systems. The design can be
compiled and simulated using open source Iverilog/GTKWave and verified using
Octave. A high level synthesis tool and GUI are designed using C#. The proposed design
tool can increase productivity by reducing the design and verification time, as
well as reduce the development cost due to the open source nature of the design
tool. The proposed design tool can be used as a standalone block generator or
implemented into current designs to improve range, accuracy, and reduce the
development cost. The generated design has been implemented on Xilinx FPGAs.
Share and Cite:
Aslan, S. , Mohammad, E. and Salamy, A. (2016) Open Source Synthesis and Verification Tool for Fixed-to-Floating and Floating-to-Fixed Points Conversions.
Circuits and Systems,
7, 3874-3885. doi:
10.4236/cs.2016.711323.
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