Positioning

Volume 1, Issue 8 (December 2004)

ISSN Print: 2150-850X   ISSN Online: 2150-8526

Google-based Impact Factor: 1  Citations  

FPGA Implementation of a Single Channel GPS Interference Mitigation Algorithm

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ABSTRACT

The FPGA (Field-Programmable Gate Array) implementation of an adaptive filter for narrow band interference excision in Global Positioning Systems is described. The algorithm implemented is a delayed LMS (Least Mean Squares) adaptive algorithm improved by incorporating a leakage factor, rounding and constant resetting of the filter weights. This was necessary as the original adaptive algorithm had stability problems : the filter weights did not remain fixed, and tended to drift until they overflowed, causing the filter response to degrade. Each model was first tested in Simulink, implemented in VHDL (Verilog Hardware Description Language) and then downloaded to an FPGA board for final testing. Experimental measurements of anti-jam margins were obtained.

Share and Cite:

G. Bucco, M. Trinkle, D. Gray and W. Cheuk, "FPGA Implementation of a Single Channel GPS Interference Mitigation Algorithm," Positioning, Vol. 1 No. 8, 2004, pp. -.

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