Author(s)

Mohamed Atri, Fatma Sayadi, Wajdi Elhamzi, Rached Tourki

Electronics and Microelectronics Laboratory, Faculty of Sciences, University of Monastir, Monastir, Tunisia..

The LPC “Linear Predictive Coding” algorithm is a widely used technique for voice coder. In this paper we present different implementations of the LPC algorithm used in the majority of voice decoding standard. The windowing/autocorrelation bloc is implemented by three different versions on an FPGA Spartan 3. Allowing the possibility to integrate a Microblaze processor core a first solution consists of a pure software implementation of the LPC using this core RISC processor. Second solution is a pure hardware architecture implemented using VHDL based methodology starting from description until integration. Finally, the autocorrelation core is then proposed to be implemented using hardware/software (HW/SW) architecture with the existing processor. Each architecture performances are compared for different data lengths.

Linear Predictive Coding; System on Programmable Chip; FPGA; Co-Design

Atri, M. , Sayadi, F. , Elhamzi, W. and Tourki, R. (2012) Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications. Journal of Signal and Information Processing, 3, 122-129. doi: 10.4236/jsip.2012.31016.