Author(s)

Yawen Wang, Sini Bin, Shikai Zhu, Xiaoting Hu^*

College of Computer Science & Technology, Jiangsu Normal University, Xuzhou, China.

The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

Advanced Encryption Standard (AES), S-Box, Tower Field, Hardware Implementation, Application Specific Integration Circuit (ASIC)

Wang, Y. , Bin, S. , Zhu, S. and Hu, X. (2024) A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard. Journal of Computer and Communications, 12, 228-246. doi: 10.4236/jcc.2024.124016.