Author(s)

Agord de Matos Pinto Jr^1,2, Raphael Ronald Noal Souza^1,2, Mateus Biancarde Castro², Eduardo Rodrigues de Lima², Leandro Tiago Manêra¹

¹School of Electrical and Computer Engineering (FEEC), University of Campinas, Campinas, Brazil.
²Eldorado Research Institute, Campinas, Brazil.

This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply V_DD = 1.8 V, the resulting set of performance parameters include power consumption P_DC = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving P_DC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.

Phase Locked Loop (PLL), Voltage-Controlled Ring Oscillators (VCRO), Dual-Delay-Path DDP, Delay Cells

Pinto Jr, A. , Souza, R. , Castro, M. , de Lima, E. and Manêra, L. (2023) Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation. Circuits and Systems, 14, 19-28. doi: 10.4236/cs.2023.146003.