[1]
|
Reliability Analysis of FinFET Based High Performance Circuits
Electronics,
2023
DOI:10.3390/electronics12061407
|
|
|
[2]
|
A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET
Circuit World,
2021
DOI:10.1108/CW-09-2019-0128
|
|
|
[3]
|
Advances in Automation, Signal Processing, Instrumentation, and Control
Lecture Notes in Electrical Engineering,
2021
DOI:10.1007/978-981-15-8221-9_107
|
|
|
[4]
|
Diseño de sumador completo rápido de baja potencia utilizando Domino Logic basado en Unión de Túnel Magnético (UTM) y Memristor
Revista Ingeniería UC,
2020
DOI:10.54139/revinguc.v27i3.148
|
|
|
[5]
|
SCDNDTDL: a technique for designing low-power domino circuits in FinFET technology
Journal of Computational Electronics,
2020
DOI:10.1007/s10825-020-01499-1
|
|
|
[6]
|
FDSTDL: Low‐power technique for FinFET domino circuits
International Journal of Circuit Theory and Applications,
2019
DOI:10.1002/cta.2627
|
|
|
[7]
|
FDSTDL: Low‐power technique for FinFET domino circuits
International Journal of Circuit Theory and Applications,
2019
DOI:10.1002/cta.2627
|
|
|
[8]
|
A novel approach for noise tolerant energy efficient TSPC dynamic circuit design
Analog Integrated Circuits and Signal Processing,
2019
DOI:10.1007/s10470-019-01444-8
|
|
|
[9]
|
Estimation and Analysis of Novel Dynamic Body Biased TSPC Design Technique
MAPAN,
2018
DOI:10.1007/s12647-018-0275-3
|
|
|
[10]
|
Low power domino logic circuits in deep-submicron technology using CMOS
Engineering Science and Technology, an International Journal,
2018
DOI:10.1016/j.jestch.2018.06.013
|
|
|
[11]
|
A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology
Journal of Circuits, Systems and Computers,
2018
DOI:10.1142/S0218126619501652
|
|
|