A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

C. ARUN, V. RAJAMANI

.

DOI: 10.4236/ijcns.2009.26064                

Abstract

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

Keywords

Viterbi Decoder, Convolutional Codes, High-Speed, Low Power Consumption, Parallel Processing, Deep Pipelining

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	H. Yang and X. Lang, “Design and implementation of high speed and area efficient Viterbi decoder,” IEEE, Proceedings of the 8th International Conference on Solid State and Integrating Circuit Technology, ICSICT’06, pp. 2108–2110, 2006.
[2]	S. Li and Q. M. Yi, “The design of high speed and low power consumption bidirectional Viterbi decoder,” IEEE, Proceedings of the 5th International Conference on Machine Learning and Cybernetics, Dalian, pp. 13–16, August 2006.
[3]	J. Jin and C. Y. Tsui, “Low-power limited-search parallel state Viterbi decoder implementation based on scarce state transition,” IEEE Transaction on Very Large Scale Integration (VLSI) System, Vol. 15, No. 10, October 2007.
[4]	C. C. Lin, Y. H. Shih, H. C. Chang, and C. Y. Lee, “Design of a power-reduction Viterbi decoder for WLAN applications,” IEEE Transactions on Circuits System I, Reg-ular Papers, Vol. 52, No. 6, pp. 1148–1156, June 2005.
[5]	R. Henning and C. Chakrabarti, “An approach for adaptively approximating the Viterbi algorithm to reduce power consumption while decoding convolutional codes,” IEEE Transactions on Signal Processing, Vol. 52, No. 5, pp. 1443–1451, May 2004.
[6]	G. Feygin and P. Gulak, “Architectural tradeoffs for sur-vivor sequence memory management in Viterbi decod-ers,” IEEE Transactions on Communications, Vol. 41, No. 3, pp. 425–429, March 1993.
[7]	P. J. Black and T. H. Y. Meng, “A 1-Gb/s, four-state, sliding block Viterbi decoder,” IEEE Journal of Solid- State Circuits, Vol. 32, No. 6, pp. 797–805, June 1997.
[8]	K. K. Parhi, “An improved pipelined MSB-first add compare select unit structure for Viterbi decoders,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 51, No. 3, pp. 504–511, March 2004.
[9]	M. H. Chan, W. T. Lee, M. C. Lin, and L. G. Chen, “IC design of an adaptive Viterbi decoder,” IEEE Transac-tions on Consumer Electronics, Vol. 42, pp. 52–61, Feb-ruary 1996.
[10]	K. Seki, S. Kubota, M. Mizoguchi, and S. Kato, “Very low power consumption Viterbi decoder LSIC employing the SST (Scarce State Transition) scheme for multimedia mobile communications,” Electronics-Letters, IEE, Vol. 30, No. 8, pp. 637–639, April 1994.
[11]	Kang and A. N. Willson, “Low-power Viterbi decoder for CDMA mobile terminals,” Conference-Paper, Journal- Article, IEEE Journal of Solid-State Circuits, Vol. 33, No. 3, pp. 473–82, March 1998.
[12]	R. Henning and C. Chakrabarti, “An approach for adap-tively approximating the Viterbi algorithm to reduce power consumption while decoding convolutional codes,” IEEE Transactions on Signal Processing, Vol. 52, No. 5, pp. 1443–1451, May 2004.
[13]	R. Tessier, S. Swaminathan, R. Ramaswamy, D. Goeckel, and W. Burleson, “A reconfigurable, power-efficient adaptive Viterbi decoder,” IEEE Transactions on Very Large Scale Integration (VLSI) System, Vol. 13, No. 4, pp. 484–488, April 2005.
[14]	M. Guo, M. O. Ahmad, M. N. S. Swamy, and C. Wang, “FPGA design and implementation of a low-power sys-tolic array-based adaptive Viterbi decoder,” IEEE Trans-actions on Circuits Systems I, Regular Papers, Vol. 52, No. 2, pp. 350–365, February 2005.
[15]	F. Sun and T. Zhang, “Parallel high-throughput limited search trellis decoder VLSI design,” IEEE Transactions on Very Large Scale Integration (VLSI) System, Vol. 13, No. 9, pp. 1013–1022, September 2005.
[16]	Y. N. Chang, H. Suzuki, and K. K. Parhi, “A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder,” IEEE Journal on Solid-State Circuits, Vol. 35, No. 6, pp. 826–834, June 2000.