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A Power Grid Optimization Algorithm by Direct Observation of Manufacturing Cost Reduction

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DOI: 10.4236/cs.2012.34046    4,324 Downloads   6,013 Views  

ABSTRACT

With the recent advances of the VLSI technologies, stabilizing the physical behavior of VLSI chips is becoming a very complicated problem. Power grid optimization is required to minimize the risks of timing error by IR drop, defects by electro migration (EM), and manufacturing cost by the chip size. This problem includes complicated tradeoff relationships. We propose a new approach by observing the direct objectives of manufacturing cost, and timing error risk caused by IR drop and EM. The manufacturing cost is based on yield for LSI chip. The optimization is executed in early phase of the physical design, and the purpose is to find the rough budget of decoupling capacitors that may cause block size increase. Rough budgeting of the power wire width is also determined simultaneously. The experimental result shows that our approach enables selection of a cost sensitive result or a performance sensitive result in early physical design phase.

Cite this paper

T. Hayashi, Y. Kawakami and M. Fukui, "A Power Grid Optimization Algorithm by Direct Observation of Manufacturing Cost Reduction," Circuits and Systems, Vol. 3 No. 4, 2012, pp. 325-333. doi: 10.4236/cs.2012.34046.

References

[1] H. Su, K. H. Gala and S. S. Sapatnekar, “Fast Analysis and Optimization of Power/Ground Networks,” International Conference on Computer Aided Design, San Jose, 5-9 November 2000, pp. 477-480. doi:10.1109/ICCAD.2000.896518
[2] K. Wang and M. M. Sadowska, “On-Chip Power Supply Network Optimization Using Multigrid-Based Technique,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 3, 2005, pp. 407-417. doi:10.1109/TCAD.2004.842802
[3] J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan and Z. Pan, “A Fast Decoupling Capacitor Budgeting Algorithm for Robust On-Chip Power Delivery,” Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, 27-30 January 2004, pp. 505-510.
[4] T.-Y. Wang and C. C.-P. Chen, “Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm,” Proceedings of International Symposium on Quality Electronic Design, San Jose, 21 March 2002, pp. 157-162. doi:10.1109/ISQED.2002.996721
[5] X. Wu, X. Hon, Y. Ca, C. K. Cheng, J. Gu and W. Dai, “Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques,” International Conference on Computer Aided Design, San Jose, 4-8 November 2001, pp. 153-157.
[6] H. Ishijima, K. Kusano, T. Harada, Y. Kawakami and M. Fukui, “An Algorithm for Power Grid Optimization Based on Dynamic Current Consumption,” International Association of Science and Technology for Development on Circuits, Signals and Systems, Vol. 531, 2006, pp. 114-119.
[7] Y. Kawakami, M. Terao, M. Fukui and S. Tsukiyama, “A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop,” The IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E91-A, No. 12, 2008, pp. 3423-3430.
[8] The Institute of Electronics and Communication Engineers, “LSI Handbook,” Ohmsha, 1984.
[9] C.-C. Chiang and J. Kawa, “Design for Manufacturability and Yield for Nano-Scale CMOS,” Springer, Berlin, 2007.

  
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