Design and Simulation of Improved SOI SiGe Hetero-Junction Bipolar Transistor Architecture with Strain Engineering

In order to improve the electrical and frequency characteristics of SiGe heterojunction bipolar transistors (HBTs), a novel structure of SOI SiGe heterojunction bipolar transistor is designed in this work. Compared with traditional SOI SiGe HBT, the proposed device structure has smaller window widths of emitter and collector areas. Under the act of additional uniaxial stress induced by Si 0.85 Ge 0.15 , all the collector region, base region and emitter region are strained, which is beneficial to improve the performance of SiGe HBTs. Employing the SILVACO  TCAD tools, the numerical simulation results show that the maximum current gain β max , the Earley voltage V A are achieved for 1062 and 186 V, respectively, the product of β and V A , i.e., β × V A , is 1.975 × 10 5 V and, the peak cutoff frequency f T is 419 GHz when the Ge component in the base has configured to be a trapezoidal distribution. The proposed SOI SiGe HBT architecture has a 52.9% improvement in cutoff frequency f T compared to the conventional SOI SiGe


Introduction
Recently, there has been increased interest in SiGe HBT technology for microwave RF circuits because of its high-frequency and compatibility with silicon technology [1]. Several works have been reported on optimizing the high-frequency of SiGe HBT that can be found from the refs. [2] [3] [4] [5]. Also, the ref. [6] has been proved that reducing the width of the emitter can greatly improve the frequency of SiGe HBT. In addition, the band structure of silicon can be changed by introducing global strain or local strain to improve carrier mobility has been reported [7] [8]. Scholars have improved the performance of SiGe HBT by using stacked metal interconnect structures or introducing mechanical stress [9] [10].
But the reliability is poor, and the process is not easy to control. A SiGe HBT device structure with a virtual substrate was proposed in ref. [11], which effectively improved the current gain. However, the improvement of frequency characteristics is limited, and the self-heating effect of the substrate is significant. Therefore, the introduction of strain engineering can reduce the transit time of carriers in the collector, and effectively improve the frequency characteristics of the device.
In this paper, the proposed device improves the frequency characteristics by introducing stress, and uses SOI substrate structure with buried oxygen layer is used to reduce the self-heating effect brought by virtual substrate. First, the SOI technology and strain silicon technology are combined to introduce uniaxial stress into the SOI collector with N + buried layer to form a new SOI SiGe HBT device structure. Then, the effects of Ge component on the current gain, Early voltage and cut-off frequency are briefly described. Finally, the structure has been proved to be able to achieve breakthroughs in the key frequency characteristics, i.e. f T > 400 GHz.

Device Model and Process Simulation Flow
In this paper, a two-dimensional device model is established by using SILVACO  TCAD tools and the ATHENA module is then employed to simulate the process flow. The proposed device architecture is shown in Figure 1.
The widths of the emitter window and the collector window are 120 nm and 400 nm, respectively, which are following the size-reduction roadmap mentioned in ref. [6]. The characteristics of the device structure are mainly reflected in the stress distribution. Firstly, the strain engineering of "embedded" Si 1−y Ge y source and drain that commonly used in 90 nm, 65 nm and 45 nm CMOS process nodes, is now introduced in the collector region, where uniaxial compressive stress is consequently applied in the horizontal direction. Then, the Si 1−x Ge x base is grown upon the strained collector. Due to the different lattice constants of Si and SiGe, the base region is subject to biaxial compressive stress [12]. According to the principle of elasticity, the collector is uniaxial compressive stressed, and the base is therefore with the act of both the uniaxial and the biaxial stresses. Also, an uniaxial tensile strained cap-layer is sandwiched between poly-silicon and Si 1−x Ge x base to build a double-layer "composite" emitter architecture [13]. The device model parameters are listed in Table 1.
The manufacture process simulation of the proposed SOI SiGe HBT mainly includes the following 6 steps: 1) Initialize (100) p-Si substrate; 2) Buried Oxide layer (BOX) is grown at 850˚C, then n + buried layer and n − collector are sequentially grown upon the BOX layer   layer where uniaxial stress generates or applies, and Si 1−y Ge y is deposited in the etched grooves by selective epitaxy growth (SEG); 4) Electrode area of the collector is etched, and heavily-doped poly-silicon as the reach-through area of the collector is deposited; 5) P-type Si 1−x Ge x base, heavily-doped P-type poly-silicon extrinsic base, and multi-layer emitter are successively deposited, and thin oxide films and poly-silicon are deposited by low-pressure chemical vapor deposition (LPCVD); 6) Aluminum (Al) film is finally produced on the whole surface by vacuum evaporation, any metal regions exterior to the electrodes are then removed by photolithography.

The Effect of Germanium (Ge) Profile on Current Gain and Early Voltage
The design of the base region is mainly considered from two aspects, one is the bandgap near to the emitter is reasonably configured to be larger than that near to the collector, so the built-in electric field is introduced to accelerate the transport of electrons [14]. The gradient Ge profile generates the acceleration field in the base, and reduces the base transition time, base recombination and increase the current.
Ge profile commonly used in the base of SiGe HBT, X 0 is the boundary of the base near the emitter, X WB is the boundary of the base near the collector, ∆E g (X 0 ) is the band narrowing caused by Ge mole-fraction at X 0 , and ∆E g (X WB ) the band narrowing caused by Ge mole-fraction at X WB . The relationship between the graded Ge fraction in the base and the current gain β is obtained by Equation (1) [15].

( )
The ratio of the current gain of SiGe HBT to that of Si BJT β max /β Si has an exponential relationship with ∆E g (X 0 ). As shown as Equation (2) The relationship between the current gain and the optimal value of the Early voltage can be obtained [15].
According to the above equations, the product of current gain and Early vol-  Therefore, the current gain of box type is the highest, which is following the above theoretical analysis.
Early voltage is one of the important parameters to characterize the electrical characteristics of devices. When the value of the Early voltage is larger, the width modulation effect in the base is smaller, and the concentration gradient of minority carrier in the base increases, hence the current gain β is naturally increased. The extraction of the value of the Early voltage is through the I C -V CE curve when I B is set to be different constant and V CE is close to zero, the tangent intersects the abscissa value, which corresponds to V A . Therefore, the smoother the I C -V CE curve, the larger the V A , and the better output characteristics of the device. When the base Ge component of SOI SiGe HBT is trapezoid-distributed, the output characteristic of the device is shown in Figure 3. The I C -V CE curves with I B = 0.05 μA, 0.5 μA, 1 μA and 1.5 μA are selected. The curve is relatively smooth, and the calculated Early voltage V A is about 186 V.    Table 2.
It can be concluded that the optimal values of current gain and Early voltage β × V A are the highest when the base Ge component is trapezoidal. Journal of Applied Mathematics and Physics

The Effect of Base Ge Component Distribution on Cut-Off Frequency fT
One of the key parameters to measure the electrical characteristics of devices is Among them, the ∆E g, grade is bandgap differences caused by gradient difference with insignificant Ge component variation. From Equation (5)

The Effect of Uniaxial Stress on Frequency Characteristics fT
The The collector of SOI SiGe HBT also affects the frequency characteristics of the device, the smaller the delay time τ c in the collector, the greater the cut-off frequency. This paper innovatively introduces the embedded Si 1−y Ge y source drain strain technology in the collector (as shown in Figure 6). When a stress is applied to the collector, the electrons velocity vertical passing through the collector region increased due to the existence of compressive stress, so the delay time of the collector region will be further reduced. The f T curves as a function of the collector for HBT device with stress and without stress are shown in Figure 7.

Conclusion
The simulation study of SiGe SOI HBT with strain into the collector. When the base Ge component distribution is a trapezoid, the influence of different base Ge component distribution on the SiGe HBT's characteristics has been simulation and analysis. The maximum value of the current gain β max is 1062, the value of the Early voltage V A is 186 V, the product of the Early voltage and the current gain is 1.975 × 10 5 V, and the maximum value of the cut-off frequency f T is 419 GHz. The cut-off frequency is increased by 52.9% compared with the device structure without stress. The proposed novel SOI SiGe HBT device is compatible with the CMOS technology and has certain theoretical significance and reference value for the circuit design and process integration of commercial terahertz Si/SiGe BiCMOS in the future.