Chip Design for In-Vehicle System Transmitter

This paper presents embedded system design of the In-Vehicle System (IVS) for the European Union (EU) emergency call (eCall) system. The IVS transmitter modules are designed, developed and implemented on a field programmable gate array (FPGA) device. The modules are simulated, synthesized, and optimized to be loaded on a reconfigurable device as a system-on-chip (SoC) for the IVS electronic device. All the modules of the transmitter are designed as a single embedded module. The bench-top test is completed for testing and verification of the developed modules. The hardware architecture and interfaces are discussed. The IVS signal processing time is analyzed for multiple frequencies. A range of appropriate frequency and two hardware interfaces are proposed. A state-of-the-art FPGA design is employed as a first implementation approach for the IVS prototyping platform. This work is used as an initial step to implement all the modules of the IVS on a single SoC chip.


Introduction
The traffic accidents are leading causes of human fatalities around the world. In 2014, the European Commission (EC) revealed that 25,900 people died in car accidents [1]. Also, the US National Highway Traffic Safety Administration has recorded 32,675 fatalities due to the road accidents in 2014 [2]. The car accidents have also resulted in losing billions of dollars each year [3]. Therefore, the transportation agencies have been concerned to decrease the human life loss in road incidents. The European Union (EU) has planned to develop and mandate the emergency call (eCall) system in all vehicles on the European roads after March 2018 [4] [5].
itiate a data link between the vehicle and the PSAP. It collects the Minimum Set of Data (MSD) that includes the information about the accident and the vehicle that are necessary for emergency aid. The MSD contains the GSP location, airbag sensor data, vehicle VIN number and other crucial data for emergency aids.
The IVS should transmit the MSD to the PSAP in less than 4 seconds [6]. As soon as the MSD is received by the PSAP, a feedback message is sent by the PSAP to acknowledge of receiving the MSD. The IVS activates the data link and voice channel between the vehicle automatically or manually through a button [6] [7].
The IVS employs multiple sophisticated modules to process the MSD data.
The MSD data is read via CAN communication in the vehicle. The IVS transmitter uses a cyclic redundancy check (CRC) algorithm and a scrambler system.
Then it encodes MSD data by a Turbo encoder module. The transmitter employs a modulator to modulate the encoded MSD in a Bipolar Pulse Position Modulation (BPPM) system [7]. The IVS transmitter needs the interface solutions to read the MSD data from the vehicle and to transmit the modulated signal via the GSM module. Developing all the modules of the IVS on a single module is challenging and needs a lot of effort to be optimized as a System-on-Chip transmitter.
Eventually, the EU eCall IVS is expected to be a chip. Designing such a chip is a challenging project because the IVS contains a complex state machine and needs to perform multiple sophisticated signal processing. Usually, the first stage of an application specific IC (ASIC) development is to design, implement and test all the functions on an FPGA. This approach is chosen by many researchers because it gives designers an excellent opportunity for optimizations [8]. Hardware implementation has shown better performance compared to software implementations for many applications [9]. Developing the IVS modules on a programmable device has not been implemented before, and it gives many advantages in terms of processing time and reliability. FPGA is highly recommended in the modern hardware design and VLSI [10] [11]. FPGA devices can be used to perform the critical processes that are used in many hardware designs [12], sensor networking [13], and image processing [14]. FPGAs give the flexibility to perform the designed modules and free designers from the cost of fabrication during the optimization process of new designs. Moreover, FPGA devices have good reconfigurability facility and allow performance tuning during the prototype phase of hardware designs [15] [16].
transmitter or receiver on a single chip. The authors in [2] analysis the updates and progress in the eCall system. They study the standardized parts of the eCall system, and they conclude that both 911 and 112 are suitable cellular links for eCall application. B. Jon et al. [5] have studied an enhanced eCall system that provided a video channel to the eCall system. Our previous published works [17] [18] [19] [20] detail the FPGA implementations of single modules of the IVS. M.
Werner et al. [7] present an in-band modem to implement the EU eCall IVS.
The approach that is employed in this work has shown good performance in hardware implementations. Researchers have employed FPGA technologies for many hardware implementations including receiver channelization [21] and embedded fuzzy controllers [22].
This work presents design and development of the IVS transmitter on a single FPGA chip. All the modules of the IVS transmitter are integrated into one module. The performance and the chip size of the designed module are optimized. Verilog HDL is employed to develop the RTL of the developed transmitter. Xilinx ISE and VIVADO tools are employed for the simulation and implementation. The results of the simulation are presented. The IVS transmitter is also developed in C code for validation purposes. The same algorithms of the developed modules are simulated in C [23]. The results that are obtained from the C code and the FPGA implementation are correlated.
The rest of this paper is organized as follows. Sections 2 details the different modules of the IVS transmitter and presents the modulation and multiplexing of the uplink waveform. In Section 3, the simulation results are presented. It also shows the hardware implementation of the IVS transmitter. In Section 4, the validation and system test results are illustrated. Section 5 discusses the employed interfaces between the IVS transmitter and the ECU as well as the GSM module. Finally, the conclusions are provided in Section 6. Figure 1 illustrates the IVS block diagram and system architecture of the IVS transmitter. The developed module is a single integrated chip that processes the functionality of the IVS transmitter. The 1120-bits of the MSD is appended with the 28 bits of the CRC parity bits. The encoded MSD data is 1148 bits. The MSD data is applied to a dedicated scrambler. The scrambler is designed based on the 3GPP standard for EU eCall system [6]. The scrambler improves the MSD data bits by reducing the long stream of zeros or ones in the MSD data. The output of the scrambler is the 1148 bits of the CRC encoded MSD. The output of the scrambler is applied to the Turbo encoder module.

The IVS Transmitter Architecture
The Turbo encoder encodes the 1148 bits of the MSD. The code rate of the  Figure 1. The In-Vehicle System transmitter structure.
The modulator groups the bits of the encoded MSD bits into three bits. Each three bit represents a symbol. There are eight (2 3 = 8) different symbols. The modulator modulates each symbol and generates a dedicated uplink waveform for it. The uplink waveform structure is detailed in [20]. The modulator starts the modulation with the synchronization signal and generates the output signal according to the 3GPP standard for the EU eCall system. The GSM module and the FPGA module are interfaced through the specific I2S that is built-in in the GSM module. The interfacing will be explained in the next sections.

The IVS CRC and Scrambler
Denote the MSD data bits by a = (a 1 , a 2 , a L ), L = 1120. The cyclic generator polynomial that is used for generating the parity bits for the IVS is represented by where T r is the time for reading the 1120 bits of the MSD, T c is the time for calculating the parity check bits for the MSD data, and T g is the time for generating the 28 parity check bits on the output port. Equation (6) shows that almost half of the processing time is saved by using the CRC parallel technique compared with the CRC serial calculation.
The employed scrambler implements the scrambling scheme based on the 3GPP standard [6]. It uses a stored scrambled sequence to scramble the CRC encoded MSD. The scrambled sequence is 1148 bits which is the same length of the CRC encoded MSD. It uses an XOR operation between the bits of the scramble sequence and the MSD data. If the MSD data contains a long stream of zeros or ones, the scrambler reduces the number of length of the zeros and ones' streams in the data. The scrambler operation can be modeled as: where S c is the output bit of the scrambler, S crc is the MSD bit, and the S SCR is the bit of scrambled sequence.
The scrambler sequence is stored in the FPGA device. The sequence is designed based on the 3GPP standards.

The Employed HARQ
The

The Modulated Signal
The modulator modulates the encoded MSD bits that consist of the RVs. Each  revision consists of 1380 bits. Each symbol represents 3 bits, so the bits of each revision are grouped into 460 symbols. The modulator modulates RV0 by generating 460 uplink waveforms. The uplink waveform starts with synchronization frame. The synchronization frame is proceeded by the data frame. The data frame is multiplexed with synchronization fragments and mute signals. The Synchronization frame, synchronization fragments, and muting signals are utilized for tracking purposes in the PSAP during detection and demodulation process. The modulation and multiplexing are designed to meet the standard 3GPP protocol for the UE eCall system.
The modulation frame contains one uplink waveform. Therefore, the modulation frame is 4 ms at 128 KHz clock frequency. The speech frame which is 20 ms contains five modulation frames.
The uplink waveform starts with the synchronization frame. The Synchronization frame starts with the synchronization tone proceeded by the synchronization preamble signal. Both the synchronization tone and preamble are developed according to the 3GPP standards for the EU eCall system.
The synchronization tone is a sine wave with 800 Hz. The wave structure is based on the proposed sine wave in the 3GPP standard for the EU eCall system it can be expressed as: 11756,19021,19021,11756,0,11756,19021,19021, 11756  . Each sample of the sine wave is represented in 16 signed bits. See Table 1.
MATLAB is used to regenerate the PN sequence as is shown in Figure 3.     Table 2.
The sine wave (Syn sin_t ) is repeated for 64 ms:

FPGA Design and Implementation
The

Simulation
The simulation of the designed IVS transmitter is presented in this section. The designed module is simulated in Xilinx ISE 14.7 which is the latest ISE version.
The simulation of the single modules is detailed in our published works [15], [16] and [17]. This work has developed all the IVS modules as a single embedded module on an FPGA device. The simulation is based on the frequency that is The uplink waveform of RV0 is simulated, and the result is shown in Figure   6. Refer to the labeling of the figure to see the different parts of the uplink waveform. Figure 6 shows that all the parts of the uplink waveform that is explained in Figure 5  The signal that is shown in Figure 6 which is the uplink waveform of RV0 (starting from M1 to M3) is repeated for eight times. Then the synchronization frames retransmitted which will be followed by another eight uplink waveforms of RV0. Figure 7 illustrates the modulated waveform of the eight revisions.
To look at the simulated waveform in more details, multiple parts of the simulated output signal are examined. Figure 8 illustrates the synchronization frame which includes 64 ms of the synchronization tone (sine wave at 800 Hz), and 196 ms of the preamble signal. The entire duration of the synchronization frame is 260 ms as is shown in Figure 9.
The sine wave Syn SIN (n) is generated based on Section 2.3. The output is in digital format. Figure 8 shows the ten samples of a complete sine wave.

Hardware Implementation
This design employs an FPGA platform to implement the designed modules.
The platform is a ready-to-use FPGA platform based on the newest FPGA technology [24]. The FPGA platform has a high capacity and a good performance.
The platform has 15,850 logic slices with 6-input Look-Up Tables (LUT) that includes 101,440 logic cells. It is a good choice to host designed chips ranging from simple combinational circuits to many sophisticated embedded processors. The functionality of the Nexys4 DDR and the FPGA device is detailed in [24]. The utilized FPGA kit is shown in Figure 10. The Verilog HDL is employed to design the modulator module. The most updated hardware development software is used to compile and synthesize the designed modules.       ule. Figure 11 also shows that all the modules of the IVS transmitter are optimized to be designed on the employed FPGA device. Therefore, the device can be employed to implement multiple modules of the IVS modem as a System-On-Chip (SoC).

Verification and Test Results
The IVS transmitter processes the MSD signal in multiple stages before the eight revisions of the encoded MSD are generated. The first stage is the CRC encoding of the MSD. Then the MSD + CRC goes through a scrambling process before it gets into the Turbo encoder. The output of the Turbo encoder is the data bits of the eight revisions (RVs). A validation method is developed to validate the designed module.
The IVS transmitter is developed in C code. The C code implements the exact algorithms that are used in the FPGA designed module. Both systems, the C code and FPGA modules, are developed according to the 3GPP standards of the EU eCall system. The outputs of both systems are correlated to validate the generated revisions of the MSD. Figure 12 illustrates the validation module that is used in this design.
If the generated encoded MSD data of the FPGA module is the same of the C code module, the output of the circuit is zero. If there is a difference between the two encoded MSD, the output of the circuit is one.  The developed IVS transmitter is tested by applying the clock frequency and WA to examine the generated output. A function generator is used to generate the clock frequency, which is 256 KHz, and WA signal, which is 8 KHz. The clock and WA signals are used to simulate the I2S of the GSM module. The output of the module is read by using a logic analyzer. The results of the test show that the module is developed as a complete IVS transmitter system. Figure   13 shows that the output of the module which is the uplink waveform is generated when WA is activated (high).
The uplink waveform starts with synchronization frame. Figure 14 shows the frame which includes the sine wave and preamble signal. Also by maximizing the uplink waveform that is generated on the output pin, one modulated waveform is shown as it can be seen in Figure 16.

The Interface Solutions
The IVS has two primary interfaces, one for reading the MSD and another for data transmission between the IVS and the GSM module. Figure 17 illustrates the structural block diagram of the IVS. The interface between the GSM module and the IVS is achieved through the I2S. The MSD can be read from an ECU through the SPI.

The IVS/GSM Interface
The designed module employs the I2S interface between the GSM and the FPGA module. The implemented I2S interface is explained in [20] [25]. However, each device has a specified I2S configuration. This design employs the I2S that is The data is transmitted on the opposite edges of the clock cycles. In both modes, there is no delay between the WA signal and the TXD signal. The RXD is half a bit delayed with respect to the TXD. The transmission is activated when WA is activated. Figure 18 illustrates the transmitted bit alignments with the WA signal.
The GSM module only works in Master mode. Therefore, the FPGA is de-     Figure 16. The uplink waveform is generated. It is verified that the generated uplink waveform is the same of the simulated waveform and the designed waveform according to the 3GPP standard for the EU eCall system.

The IVS/ECU Interface
The current design uses a build-in MSD. The MSD that is used for the test is already implemented on the test bench in a laboratory. It consists of 1120 bits. The MSD is appended with CRC, scrambled, encoded by the Turbo encoder, and then the RVs are generated. The modulator modulates the encoded bits and multiplexes the uplink signal with the synchronization frames and the mute signals. The output of the designed module is the modulation of the build-in MSD.
If the PSAP receiver receives the signal, it should be able to demodulate and decode the MSD that is known for the test.
The module is also able to read the MSD through a single digital bit as serial data. For standardization, an SPI interface is designed to read the MSD from an ECU.

Conclusions
The IVS transmitter is designed and developed as a single system on an FPGA All the modules for the IVS of the EU eCall system have been designed, synthesized, and simulated. They will be integrated on one chip and reported in the future papers.