Integrated Off-line Ballast for High Brightness Leds with Dimming Capability

This paper presents an off-line integrated full ballast to supply a 35 W assembly of Power LEDs. The proposed solution integrates an input PFC stage (a flyback converter operating in DCM) and a DC-DC output converter (a buck converter) into a single switch power stage, operating with peak current control. As it will be shown, this control scheme maintains the current through the load constant, regardless of the instantaneous value of the DC link voltage. This issue allows the use of a small capacitor for the DC link, which enhances the overall system reliability. The complete ballast has full dimming capability, and all the analysis and design steps are presented, thus ensuring the fulfilling of the existing regulations. The novelty of the final solution comes from the simplicity and robustness of the control scheme in an integrated compact single switch power stage. A final prototype of the ballast has been built and tested, and experimental results are shown in the last part of the paper. Finally, conclusions and future developments are shown.


Introduction
At present, significant efforts are being performed in the development of lighting electronic systems, as one of the major research fields related to energy savings and sustainable development.Among other causes, this is due to the continuous improvement of High Brightness (HB) and Power LEDs as outstanding light sources [1][2][3][4][5][6][7][8].In fact, these devices exhibit a continuous increase in its luminous efficiency and a high operating life and reliability.These features turn them the preferred device for an increasing number of applications [5][6][7][8].
Both the thermal and electrical behaviors of such devices make necessary the use of drivers with current limiting capability, in order to achieve stable operation The most efficient approach for this driver is the use of multi-stage Switch-Mode Power Supplies (SMPS) [9][10][11][12][13][14][15][16][17][18][19]. Figure 1 shows a typical block diagram of such a driver supplied from AC mains.
The overall components count of such drivers is relatively high, due the number of stages.Moreover, this scheme implies the use of a low ripple voltage DC link after the input Power Factor Correction (PFC) stage, commonly provided by an electrolytic capacitor.As these devices have a relatively small operating life, it penalizes the overall life span of the system [2,[20][21][22].
In this paper, a novel complete integrated electronic dimmer for Power LEDs is presented to overcome these drawbacks.The input stage of the proposed design operates from AC mains and delivers energy to a DC bus.The output stage with the proposed peak current control provides a DC current to the assembly of LEDs, regardless of the DC bus voltage.Thus, the DC bus voltage ripple can be significantly high, so the electrolytic capacitor can be removed and substituted by a small capacitance device.Provided that both power stages are single-switch topologies, the integration of the circuitry can be explored as an optimization strategy.As it will be shown in the present work, this integration is feasible, yielding to a final electronic driver with a single con trolled switch, presenting a block diagram as the one shown in Figure 2. The proposed solution allows the use of a simple and reliable control method, particularly effective in a circuit that avoids the use of electrolytic capacitors [21,22].This simplicity and robustness, along with the compact scheme inherent to integrated power stages, provides a new feasible solution for power LEDs drivers.
In addition, light dimming can also be studied as a key issue of the full ballast.The most used diming schemes, AM and PWM dimming, will be investigated applied to the resulting integrated topology.As it will be shown, AM dimming can be attained by simply changing the peak control reference, while PWM dimming can be carried out by modulating the HF switching scheme of the integrated switch.
This paper analyzes more deeply the basic scheme presented in [22].The effects of the integration in both the waveforms and the size of the power switches is considered.A revised design procedure is presented, and the design implications considering universal input line voltage condition are also presented.Both PWM and AM dimming schemes are also discussed in this paper.
The paper is organized as follows.Section 2 takes care of the power stage and the control strategy of the output converter.Later, Section 3 deals with the input PFC stage.Section 4 covers the topics related with the integration of stages and the design constraints, as well as with the effects on the input Power Factor (PF) and current harmonics.After that, Section 5 summarizes a design procedure for the full power operation of the driver.Section 6 deals with the experimental setup for the full power nominal operation of a built prototype, while section 7 takes care of both AM and PWM dimming procedures for the proposed topology.A final discussion on the extension of the design for universal AC input voltage is carried out in Section 8, while Section 9 comments on the conclusions and future developments of this work.

The Output Stage
Figure 3 shows the output stage, used in the full ballast  presented in [21].It is a reverse buck converter stage, but removing the output filter capacitor.The final circuit is formed by the inductor L, the freewheeling diode D FW and the controlled switch S. As it is shown, the current through the LEDs (modeled by the block called 'load') is the inductor current.Thus, ensuring a low AC ripple at the inductor current guarantees a proper current waveform to supply the LEDs.

The Power Stage
The operation of the converter is the same than in the usual buck converter.Although the output capacitor has been removed, the equivalent output characteristic of the LEDs assembly [23], resembles a voltage source, and thus the charging and discharging subintervals of the inductor can be considered at constant voltage [21,22].This issue allows the usual analysis of the operation of the buck converter.
Thus, the expression of the inductor current, considering Continuous Conduction Mode (CCM), can be calculated as: where i 0 and i MAX are the initial and peak value of the inductor current, respectively, u C is the input voltage, u LEDs is the output voltage, L is the inductance, and T ON and T are the turn-on time and the switching period of the switch S, respectively.
Obviously, the static gain expression of this converter can be defined as: where d is the duty ratio of the converter.
Figure 4 shows the main theoretical waveforms of this converter.
Also, the current through the switch S, i S , can be easily calculated: The average value of this input current in one high frequency switching period, i SAVG , can be obtained from (3):

The Control Stage
Different control strategies can be implemented to drive this stage.In order to supply properly the LEDs, an output current control mode must be considered.The proposed control method fixes the maximum current through the switch and the turn-off time of the switch, T OFF .Obviously, Considering ( 1) and ( 5), if T OFF and I MAX are fixed, the value of the current i 0 , and hence that of the current ripple through the LEDs, Δi LEDs , is also fixed: Thus, the i MAX -T OFF control ensures a maximum peak current value through the LEDs as well as a fixed current ripple through the LEDs.Notice how this assertion is true whatever the voltage u C is present (provided that u C is greater than u LEDs , and hence the inductor can be charged during T ON ).That is to say, for every value of u C greater than u LEDs , the control ensures a current waveform of a fixed maximum value and ripple.
Another consequence of this control is that the turn-on time of the switch, T ON , is not an independent variable of the system for the selected control scheme.From (2) and (5), T ON can be expressed as: Thus, T ON depends on the input voltage, u C , and hence the switching frequency of the converter also depends on In order to define the operation of the complete system it is interesting to express the average input current as a function of the input and output voltages as well as of the control parameters.From (4), ( 6) and ( 7), the expression of the average input current, i SAVG , can be rewritten as a function of i MAX , T OFF and u C , yielding to: So finally, it can be seen how the average input current is also a function of u C .

The Input Stage
The input PFC stage is a flyback converter, operating in Discontinuous Conduction Mode (DCM).The schematic diagram of this stage is shown in Figure 5. Prior to the integration of both stages, an analysis of the main waveforms must be carried out.The current flowing through the magnetizing inductor at the primary side of the flyback transformer, i LF , can be expressed as: where V INPK •sin() is the line input voltage, considered constant during the switching period of the flyback stage, T F ; L F is the magnetizing inductance at the primary side of the transformer; N P and N S are the turns ratio at the primary and secondary side of the transformer, respectively;

Dealing with the Integration
T ONF is the interval during which the switch S F is turned on, T d is the demagnetizing time of L F , u C is the output voltage of this stage, and i LFPK is the peak value of the current through the magnetizing inductor.This value can be described as: Figure 7 depicts the resulting full ballast, with the proposed stages connected in series.Each stage has a controlled switch, represented by a MOSFET, with its source terminal connected to ground.The integration can be carried out by equaling the switching periods of both stages and their turn-on times: ;   ONF ON F T T T T (18) Figure 6 depicts the voltage and current waveforms in the magnetizing inductor at the primary side of the transformer.
A scheme of the final ballast can be seen in Figure 8, while Figure 9 depicts the switching intervals of the integrated ballast operation.When the integrated switch, S INT , is turned on (T ON ), the input current charges the magnetizing inductance of the primary side of the transformer (Figure 9(a)).At the same time, the capacitor C provides the current that flows through the inductor L and through the load in the output converter.This interval corresponds to the turn-on intervals of the input and output stages.
On the other hand, the instant current waveform, i IN , at the input (line input current) can be easily obtained considering (10): The average value of this input current in a switching period, i INAVG , can be calculated as: After the current through inductor reaches i MAX , S INT is turned off.The magnetizing inductance at the primary side of the flyback transformer discharges through D F towards the capacitor (Figure 9(b)).Also, the freewheeling diode D FW turns on, thus discharging L through the load.At a certain time after being started, the demagnetizing of the flyback transformer ends up, and the diode D F turns off again (Figure 9(c)).Nevertheless, the output stage remains unchanged.
The current in the secondary side of the transformer, that is to say, the forward current of the diode D F , can be expressed by ( 14): The demagnetizing time, T d , can be expressed from ( 14): Thus, the average value of the output current in a switching period, i DFAVG , can be calculated as: From ( 15) and ( 16), this expression can be calculated as:  In order to dimension the switches of the proposed topology, a study of the obtained waveforms has been carried out, taking into account the requirements for the new semiconductors after the integration, S INT , D 1 and D 2 .
From the point of view of the current stresses, Figure 9(a) shows how the current flowing through S INT is the sum of the input switch (S in Figure 7) and output switch (S F in Figure 7) currents.Provided that the operation of the independent stages is the one previously discussed (Figures 3 and 6), the main current waveforms of the proposed topology are depicted in Figure 10.In fact, as it can be seen, the peak current trough S INT , i SINTPK , is the sum of both peak currents: The current waveform through diode D 1 is the same current waveform obtained for the input switch (S in Figure 7), whereas the current through D 2 is the one obtained for the output switch (S F in Figure 7).The currents through the rest of devices are the same that were obtained at the analysis of the input and output independent stages.
The analysis of the voltage waveforms is not so easy, as the voltage waveforms in D 1 and D 2 change depending on the relative value of the line instant voltage and the capacitor voltage, which in turn depends on the turns ratio, N P /N S .In order to simplify the study, it is assumed that: This assumption will be justified later, in the design section.Depending on these relative values, two different conditions of the input line voltage are present.

Relative Values of V A and V B during the Demagnetization Interval
When S INT is turned on, D 1 and D 2 are forward biased, and no voltage requirement is obtained.However, once the main switch is turned off, the resulting waveforms depend on the line instant angle, .
While the flyback rectifying diode, D F , is directly biased, the voltage at the anode of D 2 (point A in Figure 8) is defined by:   • sin On the other hand, the voltage at the anode of D 1 (point B in Figure 8), can be expressed by: as the diode D FW is directly biased, and thus withstands no voltage.Considering ( 20), ( 21) and ( 22), the relative values of V A and V B yield to:   • sin This condition reversely biases the diode D 1 , which withstands the following voltage: On the other hand, diode D 2 is directly biased, but with no current passing through.Provided that (20) is fulfilled, this condition is satisfied for every line instant.

Relative Values of V A and V B after the Demagnetization Interval
Once the demagnetization of the magnetizing inductance L F ends up, the value of V B is still represented by ( 22), but diode D F turns off, and the voltage at node A changes yielding to: Now, the relative values of V A and V B depend on the line input voltage instant.In fact, at high instant input voltage values, the following equation if fulfilled: what yields again to the condition and diodes D 1 and D 2 remain as in the previous stage.However, for low instant input voltage (near the zero crossing of the line voltage), the following equation is eventually satisfied: what yields to the opposite condition: In this case, this condition reversely biases D 2 , that withstands a voltage given by: In this case, D 1 remains directly biased but without driving forward current.
Thus, depending of the relative values of the instant line rectified input voltage and the capacitor voltage, the state of the diodes D 1 and D 2 change.The value of this capacitor, C, is the key parameter of the operation of the converter.This capacitance fixes the DC link voltage instant waveform.As the flyback input current is a function of this DC link voltage, the line input current depends also on the capacitance C. Thus, to properly design the ballast, the waveform of the capacitor voltage, as a function of the capacitance C, must be calculated.The average current in a switching period flowing into the capacitor C can be calculated.As can be seen, the input current of the capacitor is the output current of the input stage, and the output current of the capacitor is the input current through the output stage.
Thus, from ( 9), ( 17) and ( 31): (32) Considering ( 5) and (18), this current can be expressed as a function of the control parameters, i MAX and T OFF (33) The fundamental equation of a capacitor, combined with (33), yield to: (34) This differential equation must be solved numerically.The time expression of the capacitor voltage can be solved as a function of the control parameters, i MAX and T OFF , and the capacitance C: After the integration, the expression of the input line current as a function of the line angle can be expressed from ( 2), ( 8) and (13) as: (36) Finally, substituting (35) in (36), the final expression of the input current value is found, what yields to the calculation of both the power factor and the input current harmonics.

Design Procedure for 115 V RMS -60 Hz Line Voltage
This section proposes the driver, calculating the input current harmonics to verify if they fulfill the corresponding approach ideal components w The selected input is the American input mains voltage range, 115 V RMS -60 Hz, and an allowed variation of ±20% in the amplitude will be considered.At the final part of this section, once the rest of the components are designed, the rated voltage and current values of the main switches will be selected for this input condition.This will yield to a proper sizing of these devices.An additional discussion at the final part of the paper will consider the Universal input mains voltage range, and its effects on the design procedure.

Desired Operation Parameters
The first thing to settle is the target load and its nominal operation point.In this case, a 32 W assembly of Power LEDs will be the target load.The selected device is the Luxeon LXK2-PW14-U00, from Lumileds Lighting [23].To obtain such a power load, the selected assembly is formed by the series connection of 10 LEDs.In previous works, it has been demonstrated how the proposed control scheme allows a proper operation of the system, regardless the evolution of the electric and thermal parameters of the LEDs [21].
Thus, the rated electrical parameters of this load are: design procedure for a LED regulations.In a first ill be considered.
where u LEDs is the total voltage drop of the assembly of LEDs.
The design current ripple has been selected as: and, in order to keep the average forward value selected in (37), the values of i MAX and i 0 are: sin sin 2 2 Copyright © 2011 SciRes.CS ribed in previous the values of T ON , and hence of T and d, are a function of .Nevertheless, the averaged values of these parameters must be settled in order to start the design.Thus, the selected average sw ching q will be 1 kHz, du ratio w 0%: (41) th these initial design the rest of the circuit param be calculated.

Calculation of the Magnetic Com
The value of the i or at the output stage can be obt f As desc sections, it fre uency 00 whereas the target ty ill be 5  It can also be seen how prior to settle the turns ratio of the transformer, the limit values of u C must be calculated.Nevertheless, the magnetizing inductance at the primary de of the tra si e can be obtained: If an efficiency of  is considered, the maximum allowable value of the input inductor can be solved: In this case V INPK value must be the smallest possible.For the aforementioned specification of ±20% input voltage variation, now a 80% of V INPK should be selected.
From ( 41) and ( 48 After analyzing the value of u C (), it has been verified that the minimum value of C that allows a correct operation of the system is: For lower values, u C () re an u LEDs , which would imply negative currents throug n).For roperly, and the larger the C value, the smaller the DC link voltage ripple 2 (46) And finally, the average input power in a line period The latter sets the minimum PF as 0.7 for re as 0.9 for commercial applications.The values corresp tance value to verify th lications, as the PF raises above 0.9.The theoretical current har value, as well as the limits prov the maximum voltage values and C.This relationship, depicted in Figure 17, can be used to size th it can be seen, in this case the maximum voltage value fo AX , is given by: (51) Although the output stage will operate properly for capacitance values greater than C MIN , the input current will present different shapes depending on C. In order to choose an appropriate value of C, the f fi For this driver, both the limits provided by the IEC61000-3-2 a sidential and onding to the IEC61000-3-2 are given in Table 1.This table also shows the values of the theoretical current harmonics calculated for different C values.In bold letters are those values that fulfill the mentioned standard.As can be seen, the minimum capaci e standards is C = 47 µF.Moreover, this capacitance value also fulfills the Energy Star standards for residential and commercial app monics for this capacitor ided by the standard are depicted in Figure 16.
Solving (34) also provides a relationship between e capacitor.As r the selected capacitor, u CM  Also, the final turns ratio of the transformer can be designed.Considering (45), for the selected value of C, the value of the turns ratio is:

Dimension of the Power Switches
From the above discussion, the values of the absolute maximum voltage and current values for the switches of the converter can be selected considering Figure 11.Considering (51) and ( 52), the maximum voltage at the drain of the integrated switch is given by: The maximum reverse voltages in diodes D 1 and D 2 can also be calculated from Figure 11: Equations ( 53) and ( 54) have been calculated considering the aforementioned ±20% input line variation.It must also be noticed that these calculations do not consider an input clamp voltage snubber to store the energy handled by the leakage inductance of the primary side of the transformer.This snubber rises up significantly the maximum drain voltage, usually around 20% -25%, what must be considered in the final implementation.

Built Prototype and Experimental Results
A built prototype of the integrated driver has been built and tested, for the stated load of 10 power LEDs con-in the built prototype in steady state.Figure 18(a) depicts the capacitor voltage, the voltage and current through the LEDs, and the drain to source voltage at the switch S INT , for an input voltage of 100 V ( ≈ 50˚).Table 2 shows the PF and the amplitude of the input current harmonics for both the theoretical and the experimental waveforms.The experimental input current harmonics are depicted in Figure 20, along with the limits given by the IEC 61000-3-2 standard.As can be seen, the waveform fulfills these standards, although the exmenl THD is 36%, while the theoretical THD is 25%.The Figure 18 shows experimental waveforms measured e shown in Figure 19(a).As can be seen, the current hrough the LEDs is kept constant through all the l t c perimental values of the current harmonics are slightly greater than the theoretical ones.In fact, the experi ta

The Dimming Procedure
As it has been mentioned before, both AM and PWM di the main advantages and drawbacks of both strategies in the proposed ballast, and finally selects the best dimming optio

PWM Dimming
Fo ll urrent through the LEDs and the line input current, both that is to say without dimming, while Fi ntee a correct filtering of the input curre ing scheme, which yields to non-practic e integrated ballast for the selected value of 47 µF (grey), and current harmonic limits given by IEC 61000-3-2 (black) overall system efficiency is 85.8%, while the output power is 31.2W. mming schemes can be carried out in the proposed integrated ballast.This section explains n. r the PWM dimming scheme, the basic idea is to modulate the operation of switch S INT at a low fixed frequency, with a duty ratio d DIM proportional to the output light level required.Thus, a PWM dimming scheme will be obtained at the output current waveform.As the proposed topology is an integrated circuit, with only one controlled switch, the PWM diming scheme can only be implemented by completely turning on and off the fu converter.Thus, the dimming frequency is limited by the dynamic behavior of the whole ballast.The theoretical c in a line period, have been depicted in Figure 21.shows the typical PWM dimming current waveform.Notice how if this scheme is carried out, the input current would be pulsated at the dimming frequency (Figure 21(b)).Thus, the input EMI filter must guara nt, at the dimming frequency rather than at the switching frequency.In order to achieve a feasible driver, this dimming frequency should be high enough as to allow reasonable values for the EMI filter values.Figure 22 shows the LEDs current for a PWM scheme, by turning on and off the complete driver at a frequency of 500 Hz.As can be seen, the turn on and turn off transients seen in the current waveform prevent the use of higher frequencies for the dimm al too bulky EMI filters.Figure 23 shows the main waveforms of the converter for different PWM dimming ratios.Particularly, Figure 23(a) shows the input current waveforms for those dimming ratios (100%, 50% and 10%).As can be seen, the pulsating input current waveforms increase significantly the THD and decrease the PF to non-admissible values.Thus, this dimming scheme is not feasible for this topology.

AM Dimming
AM dimming scheme consists in changing the DC current level flowing through the LEDs.For this topology, it can be easily done by changing the peak current reference of the control stage, in the high frequency switching oltage.This yields to an input current and hence the THD dimming ratios.This Hence, this dimming scheme is n as the best option.
scheme.As the output current level decreases, the output power level also decreases.As the power flows through the output through the DC link capacitor, that is loaded from the input stage at twice the line frequency, a smaller power output yields to a smaller voltage ripple in the DC ink capacitor v l waveform with smaller harmonics, nd the PF increase for higher AM a can be observed in Figures 24-26, where the main waveforms of the proposed converter for AM diming ratios of 100%, 50% and 10%, respectively, are shown.It can be seen how the line input current is more sinusoidal as the diming ratio increases.It can also be seen how the voltge ripple in the DC link capacitor is also smaller for a higher dimming ratios.lected for this applicatio se

Design Considerations for Universal Input Voltage
This section deals with an analysis of the effect in the design parameters when considering Universal input voltage range in the proposed ballast.To carry out an effective comparison, it is necessary to explore which are the design parameters affected by this input margin increase.In fact, the lower limit remains constant at 115 V RMS (-20%), while the higher voltage limit considered will be 230 V RMS (+20%).The frequency range considered will be 50 -60 Hz.
The main design parameters for American and Universal input voltage ranges are presented in Table 3.
The values of the magnetizing inductance of the primary side of the transformer, L F , and the bulk DC capacitor, C, were calculated in (49) and (51) respectively for the minimum input voltage range, thus their design values are not affected by the input range increase.Analogously, the turns ratio can be calculated from (45) for the new input margin, but as the most restrictive condition comes from the smaller input voltage, this parameter also remains constant.
However, the maximum capacitor voltage depends on the maximum input voltage range, and thus this value increases significantly for the one calculated for American input range.A similar capacitor voltage plot (like the one depicted in Figure 17) can be calculated but for universal input voltage, yielding to an increase in the capacitor maximum voltage from 81 V to 130 V.   Also, the peak limit voltage values of the switches depend on this input voltage, and thus the values of u SINT_MAX , u D1AK_MAX and u D2AK_MAX can be recalculated from (53), (54) and (55) for this new voltage condition.The results of this calculations are presented in Table 3.
As can be seen, the obtained voltage ratings for the universal input voltage range, up to 900 V in the case of the integrated switch, are too high, even without considering the increase in these values that will provide the yo e of this paper, and will be addressed in ture developments.DC capacitor, 47 µF/81 V, allo sed dri waveform is relatively hi ll as the ircuit optimization to increase efficiency.There are significant losses due to the high current values at turn-off of the semiconductors.Operating the input stage in CCM would decrease those current stresses.In fact, this optimization of the efficiency has both design aspects and constructive aspects, which must be discussed in future works.clamp voltage snubber at the primary side of the transformer.Thus, this Universal input range design is bend the scop fu

Conclusions and Future Developments
A novel integrated ballast for driving power LEDs from AC mains has been presented, deeply analyzed, designed, built and tested.The proposed driver has only one controlled switch, thus obtaining a simpler and more costeffective system.Also, the obtained value of capacitance and voltage rating of the ws the use of a non-electrolytic device, which also increases the reliability of the whole ballast.The propo ver also allows AM dimming very easily, which is enough for a number of applications with no special constraints in color rendering, which are the target uses for this converter (e.g.emergency lighting systems, street lighting, etc.).
The main drawbacks are the low efficiency and the high stresses of the electronic devices.Also, and although the input current fulfills the harmonic regulations, the harmonic distortion of this gh.Another drawback is the lack of galvanic isolation due the integration process, although this drawback is not as critical as it could be in other kind of lamps (for instance HID lamps, where very high input voltage pulses must be provided to the lamp).
Future developments include a deep study of the design for Universal input voltage range, as we c , and Science Office (MCINN), unde grant no.DPI-2007-61522, project "BENAPI", and by the European Union through the ERFD Structural Funds (FEDER).

Figure 1 .
Figure 1.Block diagram of an offline electronic driver for Power LEDs.

Figure 2 .
Figure 2. Block diagram of an integrated electronic driver for Power LEDs.

Figure 3 .
Figure 3. Scheme of the output stage

Figure 4 .
Figure 4. Main waveforms at the buck converter.

Figure 5 .
Figure 5. Schematics of the flyback input stage.

Figure 6 .
Figure 6.Main waveforms in the magnetizing inductor at the primary side of the transformer of the input stage.

Figure 10 .
Figure 10.Main current waveforms at the proposed topology.

Figure 11 (
a) depicts the voltage waveforms for high instant line voltage, given by (26), while Figure 11(b) shows the voltage waveforms for the alternate low instant line voltage condition, defined by (28).

Figure 11 .
Figure 11.Main voltage waveforms at the proposed topology.(a) High line instant input voltage condition.(b) Low line instant voltage condition.
calculated considering the quation that expresses the average input power in a switching period.Considering (36), the instant input power as a function of the line angle, , can be calculated as:  Notice how in (44) and (45) the V INPK value is the highest possible.For instance, considering the ±20% input line variation, in this case a 120% of V should be selected.

5 . 3 .
), and considering  = 0.85, the magnetizing inductor L F is: Solution of the Equation of the Capacitor Voltage aches voltage values smaller th h the LEDs (obviously an impossible conditio greater capacitance values, the system operates p , as shown in Figure 12.Equation (34) has been solved numerically for different capacitor values.The obtained voltage waveforms at the capacitor, u C , have been plotted in Figure 12.

Figure 12 .
Figure 12.Theoretical wavefo u C , as a function of different capacitance values.rms of the capacitor voltage, Figure 13 plots this input current for different values of C. As can be seen, the current trends to be sinusoidal for high values of C, while high distortio f PF and Figure plots both parameters as a function of C. The amplitudes of the line current harmonics, as a funct have been obtained, and they are shown in Figure 15.

13 .
Figur re e 13.Theoretical waveforms of the AC line input curnt, i IN , as a function of different capacitance values.

Figure 14 . 1 Figure 16 .Figure 17 .
Figure 14.Theoretical values of PF (filled line) and THD (dotted line) of the input current, for different C va lues.
Figure 18(b) shows these waveforms for an input voltage of 162 V ( = 90˚) The line frequency waveforms of the prototyp are ine ycle, although the capacitor voltage, u C , presents a significant voltage ripple.Figure 19(b) plots the experimental and theoretical waveforms of the capacitor voltage, u C , and the line input current, i IN .As can be seen, the experimental waveforms are in good agreement with the expected values.

Figure 19 .
Fig ef the built prototype, at different line angles.(a) V IN = 100 V ( ≈ IN

Figure 21 (
a) shows the theoretical line and LEDs currents at full power operation, gure 21(b) shows the same waveforms if operated under PWM dimming scheme (modulated with a low frequency).In fact, Figure 21(b)

Figure 21 .
Figure 21.Current through the LEDs, i LEDs , and line input current, i IN , dimmin ; for a line period.(a) without PWM g (b) with PWM dimming.
This work was supported by the Spanish Government Innovation r research "Impact of Dimming White LEDs: Chromaticity Shifts Due to Different Dimming Methods," 5th International Conference on Solid State Lighting, Bellingham, 1 August 2005.doi:10.1117/12.625924