A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer

This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.


Introduction
With CMOS scaling, the performance of digital circuits has been improved dramatically.Analog LSIs operating in the millimeter wave frequency and the THz region also appeared owing to the improvement in the cut-off frequency by scaling.On the other hand, negative aspects due to scaling, that is, the drop in the intrinsic gain, the increase in device variation, and the decrease in the signalto-noise ratio due to low supply voltage, are revealed.Various techniques for overcoming these challenges have been studied.A time-domain approach that expresses an analog signal in the time domain has especially attracted much attention.Time-domain signal processing is advantageous in that the signal expression is not limited to the supply voltage and in that most circuits can use digital circuits; therefore, it can enjoy the benefit of CMOS scaling.For example, the implementation of a time amplifier was discussed in [1] [2].The time am-plifier with the gain of 4.8 was obtained using cross-coupled chains of variable delay cells.Moreover, a time adder and subtracter using a time register were reported in [3].Inspired by this technology trend, many works have tried to introduce time-domain processing into analog-to-digital converters (ADCs).An ADC using time-domain processing is called a time-based ADC (TB-ADC).A few works using a VCO as the voltage-to-phase converter measured the phase in the time domain [4] [5].They have a high resolution but a narrow band due to the noise-shaping property in time quantization.In [6] [7], a simple architecture based on a voltage-to-time converter (VTC) and a time-to-digital converter (TDC) were reported.The input voltage signal is converted into pulses with a delay between them, proportional to the input voltage by the VTC.Then the delay is measured by the TDC.This architecture can achieve a high sampling frequency; however, the nonlinearity of the VTC limits the resolution.In a recent publication, hybrid converters have been described that use both the conventional voltage-domain and the time-domain quantizers [8] [9].These works successfully reduced the power dissipation using the time-domain quantizer; however, the sampling frequency was limited to less than 100 MHz.
As mentioned above, a TB-ADC with a high resolution and a high sampling frequency has never been developed; therefore, we aimed to realize an 8-bit, 500-MS/s TB-ADC.In this paper, the problems in the conventional TB-ADC are discussed in Section 2.Then, a novel TB-ADC combining a flash ADC and a ring-oscillator-based TDC is proposed in Section 3, followed by the measurement results of a test chip in Section 4. Finally, Section 5 concludes this work.

Challenges in Conventional TB-ADCs
Figure 1 shows a block diagram of a 5-bit TB-ADC using a VTC and a TDC [10].The input signal is converted into a train of pulses by the VTC whose output is fed into the TDC, which converts the delay between pulse edges into a digital representation.This ADC uses a folding architecture to reduce the power dissipation of the TDC.The output signal of the VTC is also fed into the folding Figure 1.Block diagram of 5-bit TB-ADC using VTC and TDC [10].phase detector (FPD), which detects the sign of the input signal.The PFD output is used as the most significant bit of the ADC output as well as the folding signal that controls a multiplexer (MUX).This enables to halving of the input range of the TDC, whose resolution can be reduced by Therefore, a high-resolution ADC architecture combining conventional voltagedomain processing and time-domain processing is proposed.Figure 2 shows a block diagram of a 10-bit TB-ADC using subranging architecture [11].The comparator and CDAC should operate seven times in the SAR ADC.Additionally, the VTC uses a high supply voltage (2.5 V) to improve the linearity performance, resulting in an increase in power dissipation.

Proposed ADC Architecture
As mentioned in Section 2, the high-resolution ADC can be obtained by a combination of the voltage-domain and the time-domain processing; however, the sampling frequency is low.This is because the SAR ADC is used as the voltage-  The flash resolution of 3 bit is used to prioritize the circuit area in this design.No offset calibration technique is used for the comparator because the area of the calibration circuit is often considerably large.The range overlapping technique [13] is used instead.The offset voltage of the comparator affects the residue generation as shown in Figure 6.The residue is in the range from 0 to V FS /8 when the comparator has no offset, where V FS is the input full scale range.However, the residue exceeds V FS /8 when the comparator has a positive offset.On the contrary, the residue has a negative value when the comparator has a negative offset.Therefore, the TDC should cover more than V FS /8.The input range of the TDC is extended to V FS /4 and has 6-bit resolution in this implementation.

VTC
A schematic of the VTC is shown in residue signal is set to V DD /2 (500 mV).The highest residue signal is 563 mV (V DD /2 + V FS /8) and is discharged to the common level and the STOP signal is generated by the CT-CMP when the residue signal reaches the common level.
The current mirror circuit is connected to V resp through a switch in the conventional circuit; therefore, the output voltage of the current mirror circuit (V cm ) is lower than V resp .Therefore, V cm is 440 mV, and the output resistance of the current mirror circuit is 30 kΩ when V resp reaches 500 mV.On the other hand, the current mirror circuit is connected to V resp through a capacitor C rp , and V cm is precharged to V DD when the START signal is low; therefore, V cm starts to ramp from V DD .V cm is 810 mV, and the output resistance of the current mirror circuit is 530 kΩ when V resp reaches 500 mV.The C-coupled current mirror successfully enhances the output resistance, resulting in highly linear ramp operation.
The CT-CMP detects a cross point of V resp and V resn .Its output (STOP) rises when V resp becomes lower than V resn .The time between START and STOP is proportional to V resp -V resn ; therefore, the voltage signal can be converted into the time signal.The CT-CMP is composed of a two-stage amplifier.The first stage is a high-gain differential inverter amplifier, and the second stage is a current-mirror-loaded pMOS differential amplifier.The high gain of the first stage successfully reduces the input referred noise to 5 nV/√Hz.
A block diagram of the TDC is shown in Figure 9.A two-step architecture [14] is used; that is, a coarse time measurement is performed by counting the ring oscillator's (RO) output, and a fine time measurement is performed by looking at the RO's phase.The coarse and fine measurement results are combined by the TDC encoder, and the 6-bit binary code is output.The pMOS and nMOS gate widths of the RO are 1.2 μm and 0.4 μm, respectively, and the time resolution of the TDC is 11 ps.The nine-stage RO is used to get the minimum power dissipation.A power-hungry, high-frequency counter such as a common-mode logic circuit [15] is required when the number of stages is too small because the output frequency of the RO is too high.On the contrary, the power dissipation of latches becomes large when the number of stages is too large.The nine-stage RO is optimum in this design.The counter is composed of a true sin gle-phase clock FF to reduce power dissipation.
The rising and falling delay times of the inverter in the RO are designed to be equal; however, the delay time changes because of the process deviation as shown in Figure 10.An ununiform delay time causes a conversion error.This can be alleviated by shifting the logical threshold voltage (V TH ).The delays are made uniform by increasing V TH in the example shown in Figure 10  V TH in the V TH set phase.Then, the RO < I > is sampled at the falling edge of CK, which is synchronized to the STOP signal.The sampled signal is transferred to theOL node, then the regeneration latch is activated; thus, the sampled voltage is compared with V TH .The automatic V TH adjustment circuit was not implemented in this version yet, and the V TH was adjusted manually.The implementation of the automatic V TH adjustment is planned for future work.

Experimental Results
A test chip was fabricated using 65-nm digital CMOS technology to demonstrate the effectiveness of the proposed architecture.Figure 12 shows a photomicrograph and a layout plot of the test chip.The circuit area of the ADC core was 180 μm × 190 μm.The chip consumed 2.0 mW at 500 MS/s, and the supply voltage was 1 V.The chip was mounted on an evaluation board by using short bonding wire, resulting in a small parasitic inductance.The analog input signal and the clock signal were fed through SMA connectors.Figure 13      were down-sampled by a factor of 3 because of a limitation in the maximum bit rate of the logic analyzer used.The harmonic distortion was sufficiently small, and a high SFDR of 56.0 dB was observed.Relatively large harmonics was observed for the input frequency of 11 MHz.This is due to the signal generator for the input signal which has rather poor signal purity in the low frequency range.
constant conversion time regardless of the resolution.On the contrary, the conversion time of the TDC based ADC exponentially increases when the resolution increases.Therefore, the sampling frequency is improved as the flash resolution increases.The sampling frequency is limited by the TDC in this architecture.The power dissipation has a minimum value around a flash resolution of 2 to 4 bit.This is because the power dissipation of the flash ADC increases and that of the TDC decreases as the flash resolution increases.Therefore, the conversion energy has a minimum value around a flash resolution of 3 to 5 bit.

Figure 11 .Figure 9 .Figure 10 .
Figure 11.The output nodes of the regeneration latch OR, OL are precharged to

Figure 11 .
Figure 11.Schematic of latch circuit with threshold-adjust function.

Figure 12 .
Figure 12.Photomicrograph and layout plot of test chip.

Figure 15 .
Figure 15.Measured spectra at sampling frequency of 500 MHz.

Figure 16
Figure 16 shows the sampling frequency dependencies of the FOM.The minimum FOM of 32 fJ/conversion-step was obtained at the sampling frequency of 500 MHz and the supply voltage of 1 V.At the supply voltage of 1.1 V, the FOM increased to 43 fJ/conversion-step at 650 MHz.Table 1 shows a performance comparison among the ADCs recently published [10] [11] [16] [17].The FOM of this work is superior to other TB-ADCs.The FOM of [16] exhibits better value than this work; however, it used 45 nm CMOS technology.