Investigation of Electrical Transport in PECVD Grown aSiC x : H Thin Film

Dc/ac transport characteristic of PECVD grown hydrogenated amorphous silicon carbide (a-SiCx:H) thin film was investigated in MIS (metal/insulator/semiconductor) structure by dc current/voltage (I/V) at different temperature (T), ac admittance vs. temperature at constant gate bias voltages and deep level transient spectroscopy (DLTS), respectively. According to I-V-T analysis, two main regimes exhibited. At low electric field, apparent Ohm’s law dominated with Arrhenius type thermal activation energy (EA) around 0.4 eV in both forward and reverse directions. At high field, on the contrary, space charge limited (SCL) current mechanism was eventual. The current transport mechanisms and its temperature/frequency dependence were interpreted by a thermally activated hopping processes across the localized states within a-SiCx:H thin film since 0.4 eV as EA was not high enough for intrinsic band conduction. Instead, transport of charge carriers took place in two steps; first a carrier is thermally excited to an empty energy level from an occupied state then multi-step tunnelling or hopping starts over. Therefore, the two steps mechanisms manifested as single activation energy, differing only through capture cross sections. In turn, two steps in capacitance together with conductance peaks in C-(G)-T while convoluted DLTS signal associated with such events in the measurements.


Introduction
Both tunability of energy band gap from 1.9 -3.2 eV with different carbon content (x) [1] and n-/p-type dopability by appropriate doping gases [1] lead an opportunity of amorphous hydrogenated silicon carbide (a-SiC x :H) films to be used in solar cell technology and light-emitting diodes (LED's).In former, owing to the excellent surface passivation of crystalline silicon (c-Si) and large area deposition capability, a-SiC x :H films are used in silicon solar cell applications.Recent works have shown that Si-rich a-SiC x :H films with low power regime possesses brilliant electronic surface passivation in silicon heterojunction solar cells [2][3][4][5][6][7][8].Improvement in silicon heterojunction solar cells to achieve high conversion efficiency (greater than 22%) [9,10] is possible by electronic surface passivation, i.e., low recombination loss of photo-generated carriers.
Contrary to that LED's applications require bipolar carrier transport and efficient recombination rate of injected electron-hole pairs within the intrinsic layer of a-SiC x :H films.Each phenomena, transport and/or re-combination issues, limits the efficiency of LED's in which carriers might flow through either localized or extended states via hopping [11] in a-SiC x :H films.Within this context, since carrier injection issue and nature/amount of localized density of states (DOS) distribution are tightly bound with each other, d.c. and a.c.conductivities seem to be convenient techniques for characterizing electrical features of the a-SiC x :H film within a metal/insulator/semiconductor structure.In other words, d.c.current/voltage (I/V) at different temperatures, a.c.admittance (Y = G + jωC, G = conductance, C = capacitance, and ω = frequency) versus bias voltage and/or temperature at constant gate bias voltages and deep level transient spectroscopy (DLTS) are proper techniques to employ for investigating electrical features of a-SiC x :H film in MIS structure.

Film Fabrication and Experimental Detail
a-SiC x :H film studied in this work was grown, under the mixture of 30 ccm SiH 4 (silane) and 30 ccm C 2 H 4 (ethylene), by 13.56 MHz plasma enhanced chemical vapor x deposition (PECVD) technique where the deposition parameters were held at 0.1 Torr pressure, 250˚C substrate temperature, 60 mW/cm 2 ac RF power.p-type silicon wafer with resistivity of 10  cm, and corning 7059 glass plates were used as substrates for electrical and optical analyses.
A profiler (Ambios XP-2) was used to measure the film thickness as 125 nm.UV-VIS spectroscopy (Perkin Elmer Lambda 2S) supplied the optical energy gap and refractive index as 2.67 eV and 2.15, respectively, d.c and ac electrical measurements were performed by an electrometer (Keithley 6517), an impedance analyser (HP 4192 A), and DLTS (Semilab DLS 82 E), respectively.

d.c. Properties Through Resistivity Measurements
Electrical resistivity of the film has been obtained in sandwich configuration from the ohmic region of the dc current (I) vs d.c voltage (V) and depicted in Figure 1 (a).Apart from the existence of the ohmic region in forward current, another conduction mechanisms, depending on the magnitude of bias voltage, are eventual.Along the I-V curve, ohmic region, is followed by a superlinear region.Forward current is proportional to power of bias voltage; i.e., p I V  where p inversely varies with temperature.It is located between 2.2 and 3.4 for the exploited temperature interval of 295 -370 K.This power law dependence of the current on the applied voltage beyond a critical value indicates a space charge limitation.
Conductivity, evaluated from the ohmic region follows an Arrhenius behavior with a single activation energy (E A ) of about 0.4 eV within the studied temperature interval (see Figure 1(b)).Typically, the ohmic region is attributed to an intrinsic thermal excitation of free carriers.However, for a wide energy gap insulator at moderate temperatures as in this case, it is doubtful.Rather, a hopping type conduction through the localized states is reasonable owing to the presence of large amount of distributed localized states on either side of the Fermi level (E F ).In other words, the electrical conduction take place in two steps; in first, thermal excitation of carrier from E F to the relevant edge of the extended state band, and then hopping across the localized states whose density strongly increases (exponential or Gauss like) away from E F towards the band edges.That is, the thermal excitation allows carriers to populate the states at energies distant from E F and thus strongly in- creases the number of neighboring states accessible for hopping (lower hopping distance and higher hopping rate) [12][13][14][15][16]. Within this context, the large majority of transport occurs within a relatively thin energy interval whose median value is defined as the so called average transport energy E t : ) appears as the measured activation energy (E A ) from the Arrhenius plot (Figure 1-b).The medium activation energy value of 0.4 x eV for dc conductivity is neither high enough for intrinsic band conduction nor low enough for hopping transport across the uniformly distributed deep states.

a.c. Properties Through Admittance Measurements
Admittance measurements on the MIS structure (Al/a-SiC x :H film/p-Si/Al) were performed as a function of dc gate voltage (V G ), temperature (T) and frequency (ω) of the gate voltage modulation to carry out the dielectric behavior of the a-SiC x :H film.

Capacitance (Conductance)-Bias Voltage
Variation Figure 2 exhibits the strong ω dispersion of both measured parallel capacitance (C m ) and conductance (G m /ω) as a function of V G .Apart from the frequency dependence, C m converges to a voltage independent value of about 500 pF at the negative side of V G under high frequency.This is relevant to strong accumulation in the silicon interface and corresponds to the film geometrical capacitance where film thickness d I was measured separately as 125 nm by both mechanical profiler and UV-Visible transmittance within mutual checking [16].C f value of 500 pF supplies the film dielectric constant as The frequency dependence of the admittance along the accumulation bias voltage is originated from the modulation of injected charges, t , residing interior of the a-SiC x :H film.Because, under an accumulating type V G , the stored holes at the a-SiC x :H/p-c-Si interface are injected by multi-tunneling (or hopping) through localized states due to the direction of applied electric field.Therefore, a charge modulation  is located at an average distance d I -x t with x t being the average distance of interior injected charges from the p-c-Si side.Hence, the measured capacitance is "build" by these charges due to the moment arm (centroid of charges) as: Increase in ac modulation causes reduction in Q t , in turn d enlarges, leading to a reduction in capacitance from geometric value to the first minimum; forming a first step in C-V curve (see Figure 2(a)).The following section is devoted to figure out a second step in the measurement.
The amount of injected charges within the a-SiC x :H film bend the silicon energy bands, s  .Equality of s  to zero   0 s   corresponds to compensation of injected charges and marks the boundary between end of accumulation regime and onset in depletion regime.In other words, conventional MOS analysis predicts the depletion regime subsequently after the accumulation x one as V G is swept towards more positive side.Additionally, the involvement of charges, either in a-SiC x :H or a-SiC x :H/p-c-Si interface, modify the shape of C-V curve.Manifestation of this issue in C-V curves appears as steps with frequency dependent manners.The first step is interpreted as the modulation of injected charges over the geometric film capacitance under a condition of 0 At low frequency,  4(a-b) at the gate bias of -1 V corresponding to depletion/weak inversion regime.Frequency dependent capacitance steps of C m as well as G m /ω peaks are distinguished within 200 -280 K and 280-340 K temperature intervals.These temperature activated processes are Arrhenius type (see Figure 5).It is worth to note that determined E A from the steps in capacitance remains at the same energy values but appear at different temperature interval in C-T scans, as shown in Figure 4.Moreover, at a temperature range following the second step, frequency dependent capacitance plateau arises for a-SiC x :H film and designates the film geometric capacitances at high frequency as in C-V curve.
Variation of capacitance as a function of bias/temperature could be interpreted equivalently with capture/emission time,   release time of trapped charges within the film to the valance band edge via interface states (that is, a two step mechanism) [18];

DLTS Measurement
A small signal (or energy resolved) DLTS measurement is performed and depicted in Figure 6 for a-SiC x :H film in MIS structure at hand.In the measurement, a small injection pulse is superimposed on a quiscent voltage (U quiscent ) which defines the position of the Fermi level at the surface of p-c-Si.Moreover, the measurement involves the periodic application of small filling voltage (U fill ) of width t p to charge/discharge the interface traps around E F with majority carriers in depletion regime.The capacitance transient of DLTS signal of the present system is expressed as [19]     where T p is the period of applied trap filling pulse, t g = t p + t d with t d = T p /20 and  is the relaxation time.
As shown in Figure 6, convoluted DLTS signal of peaks become to separate as V G increases.Remarkably, from the peak of the temperature position, Arrhenius plot is drawn to determine E A while height of the signal serves to evaluate the interface state density.Similar to C-T scans, two series of peaks lead to same E A (see Figure 5), differing through only capture cross sections.Also, movement of peaks as bias changes are the signature of interface traps rather than bulk nature, reinforcing the above analysis.

Conclusions Conclusions
Apart from I-V-T analysis, C-T-ω/DLTS measurements have stated that the obtained E A was the same for the first and second steps/peaks, respectively.This was interpreted as the traps lying on the same energy value at the interface around the Fermi level leading to the same activation energy and appearing at shifted along the 1/T axis.
Apart from I-V-T analysis, C-T-ω/DLTS measurements have stated that the obtained E A was the same for the first and second steps/peaks, respectively.This was interpreted as the traps lying on the same energy value at the interface around the Fermi level leading to the same activation energy and appearing at shifted along the 1/T axis.

Figure 1 .
Figure 1.(a) Forward current-forward bias voltage characteristics of a Al/a-SiC x :H/p-c-Si MIS structure at studied temperature interval of 295 -365 K. Two main conduction regimes, ohmic and space-charge-limited (SCL), are clearly observed.The inset of the figure reinforces the existence of SCL mechanism, (b) Temperature dependence of saturation current in forward direction and reverse current at a bias of 0.1 V.The activation energy, determined via the slope of the variation, was determined at the proximity of 0.4 eV in both directions.
distance of d I from the interface, whereas t Q

Figure 2 .
Figure 2. Capacitance (a), conductance/frequency (b) variations as a function of gate bias voltage at room temperature under various modulation frequencies for Al/a-SiC x : H/pc-Si MIS structure.
charge and N A denotes doping concentration of c-Si.Consequently, d in this case would be expressed by

3 . 2 . 2 .
, moment arm shifts from d I -x t to d I .For high frequency where modulation exclusively occurs at the silicon depletion edge so d I moves to d I + d D .Consequently, two steps in capacitance are formed in C-V analysis.Capacitance (Conductance)-Temperature Variation Temperature dependence of admittance measurements (C m and G m /ω) under predetermined dc gate biases and small amplitude ac excitation frequency of 1 kHz for a-SiC x :H film in MIS structure is illustrated in Figures 3 a-b and 4 a-b, respectively.The mechanisms behind the capacitance steps are investigated through frequency dependence; examples for a-SiC x :H film is given in Figure

Figure 3 .
Figure 3. Capacitance (a), conductance/frequency (b) vs. temperature scans at various gate bias voltages (-3, -1 and +1.5 V) at 1 kHz meauring frequency.changing gate bias (temperature) towards accumulating bias regime (high temperature zone) leads to a decrease in s  , hence only fast states could follow the ac modulation.Increasing the gate bias values towards positive side, the flat band voltage   0   sis first reached and then the depleting gate bias regime starts.Further increase in gate bias causes the increase of s  (>0) in turn widening the depletion width.This phenomenon appears as steps in C m and peaks in G m /ω.These steps might be correlated as follows: first, the trapped holes in a-SiC x :H film hop or multi-tunnel toward interface states, then emitted from the interface states to the valance band edge of c-Si substrate.Hence, two characteristic times