A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator

A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.


Introduction
Power reduction in a medium resolution and high-speed analog-to-digital convertor (ADC) is strongly required for front end of wireless systems and read channels of disk systems.The power consumption of a CMOS circuit is proportional to the square of the supply voltage; therefore, reducing the supply voltage is the most effective method for reducing the power consumption.However, supply voltage reduction and high-speed operations are incompatible because the delay time is significantly increased when the supply voltage is simply reduced.Thus, it is important to select a suitable circuit architecture that can run at a low supply voltage.Successive approximation registers (SAR) and flash ADCs are mainly used for medium resolution and high-speed applications.A SAR ADC uses a low amount of power and covers only a small area; however, a comparator should be used the same number of times as there are bits [1]- [3].For example, an operation speed of more than 6 GHz is required for the comparator in a 6-bit, 1-GHz SAR ADC.Therefore, the SAR ADC is unsuitable for use in low voltage operations because the operation speed of the comparator is degraded due to the low supply voltage.On the other hand, a flash ADC is tolerant of the speed degradation in the comparator because the comparator is used only once for the conversion [4]- [6].Therefore, several previous works on low-voltage and high-speed flash ADCs have been conducted [7] [8].These ADCs run on a 0.5-V supply voltage; however, the sampling frequencies are 600 MHz and 420 MHz, which are insufficient values for the above-mentioned applications.The sampling frequency of a flash ADC running on a 0.5-V supply voltage is limited by the comparator delay; therefore, reducing the comparator delay is essential for enhancing the sampling frequency.
We discuss the speed limiting factors of the conventional comparators running on a 0.5-V supply voltage in Section 2. We then propose our temporarily boosted comparator for reducing the delay time while maintaining a low power consumption in Section 3. Finally, we show the simulation results of a designed flash ADC by using the proposed comparator.

Problem with Conventional Low Voltage Comparators
A conventional comparator running on a 0.5-V supply voltage is shown in Figure 1 [7].This type of comparator is referred to as a double-tail analog latch (DTAL).This circuit is composed of two stages.The first stage is a dynamic amplifier and the second one is an analog latch.During the reset phase (CK = 0), the outputs of the dynamic amplifier (AOP and AON) are precharged to the V DD and the outputs of the analog latch (OUTP and OUTN) are reset to GND.The voltages of the AOP and AON drop to GND when the CK rises to the V DD and the phase shifts to the comparison phase.The falling rates of the AOP and AON depend on the input voltages, so the voltage difference between them is generated according to the difference in input voltage.The voltage difference between the AOP and AON is latched by the second stage, and thus, the digital signals (OUTP and OUTN) are output.The forward body bias technique is used to enhance the speed performance.The body voltage is 0.5-V forward biased to reduce the threshold voltage.This enables the delay time of the comparator to be reduced even when the supply voltage is 0.5 V. Special consideration is required for the offset calibration in the low supply voltage region.The MOS varactor is widely used to compensate for the offset voltage of the dynamic comparator [9].However, the offset compensation range decreases as the supply voltage is reduced because the change in capacitance of the MOS varactor is reduced in the low supply voltage region.Therefore, an offset cancellation technique using a variable delayer was adopted in the previous work shown in Figure 1.The activation timing of the dynamic amplifier is controlled by the variable delayer for the offset calibration.For example, let the threshold voltage of M1 be higher than M2.The falling rate of the AOP is slower than that of the AON when the input voltages are equal because the drain current of M1 is less than that of M2.The delay time of the delayer of CKN is increased to compensate for the delay difference between the AOP and AON.The offset voltage can be completely compensated for by properly adjusting the delay time.However, the minimum delay time of the delayer is significantly large because the delayer is composed of a two-stage inverter; therefore, the delay time of the comparator is large.Moreover, the noise voltage of the comparator is also relatively large because the jitter of the delayer is large.
Another conventional comparator, which is shown in Figure 2, overcomes the above mentioned problems [8].A varactor comprised of metal oxide metal (MOM) capacitors and MOS switches are used to compensate for the offset voltage.The capacitance can be changed by connecting and disconnecting the MOM capacitor using the MOS switch.This method can provide a sufficient change in capacitance to compensate for any offset voltage.This comparator can achieve a smaller delay time and noise voltage compared with the comparator shown in Figure 1.However, the delay time is still too large for use in a GHz sampling flash ADC.
The simulated V DD dependences of the delay time and power consumption of the conventional comparator using the MOM capacitor and MOS switch are shown in Figure 3.The simulation is performed by using 65-nm CMOS technology.The t pd_amp and t pd represent the delay time of the dynamic amplifier and that of the entire comparator, respectively.The t pd_amp is defined as the time between a 50% CK rising edge and a 50% AOP or AON falling edge.The t pd is defined as the time between a 50% CK rising edge and a 90% difference in the OUTP and OUTN.The power consumption can be successfully reduced as the V DD is decreased.The power consumption at V DD = 0.5 V is decreased to approximately 1/4 that at a V DD = 1 V.The t pd_amp is almost constant even when the V DD is decreased, because the operating current of the dynamic amplifier is not determined by the V DD but by the common level of the input signals.On the other hand, the t pd rapidly increases when the V DD is decreased because the delay time of the latch circuit strongly depends on it.

Temporarily Boosted Comparator
The supply boosted comparator (SBC) was reported to reduce the delay time under low supply voltage condition [10]- [12].It attained high-speed operation by boosting the supply voltage locally.However, the current biased comparator was used in the SBC; therefore, the large boost capacitor was required.We apply the boosting technique to the dynamic comparator shown in Figure 4; thereby, sufficient boosted voltage can be obtained by the small boost capacitor.The proposed comparator is based on a stacked analog latch (STAL) to reduce the power consumption.
The delay time of the STAL is approximately the same as that of the DTAL; therefore, a temporarily boosted technique is combined with the STAL (TB-STAL) to reduce the delay time.A boost circuit is connected to the V DD terminal of an analog latch and reset pMOSs are connected to the normal V DD .The boosted V DD (V DDB ) can be supplied to only the analog latch and only in the comparison phase.This enables for the reduction of the delay time while keeping the power overhead to a minimum.The operating waveforms of the proposed comparator at the supply voltage of 0.5 V are shown in Figure 5.In the reset phase (CK = 0), the V DDB is equal to the normal    V DD .Then, when the CK rises, the boost control signal (BST) rises, and thus, the V DDB is boosted by the boost capacitor (CB).The peak voltage of the V DDB is approximately 0.65 V.This accelerates the transition of the OUTP and OUTN.The stored charge in the CB is consumed to charge the parasitic capacitance of the OUTP and OUTN; therefore, the V DDB returns to the normal V DD .The capacitance of the CB should be designed so that the high level of the OUTP and OUTN is nearly equal to the normal V DD .
Body bias control calibration [13] is used to compensate for the offset voltage.In this technique, no additional circuitry is added to the dynamic amplifier; the control voltages (V calp and V caln ) are connected to the body of the differential MOS transistors (M1 and M2).This method does not introduce any additional capacitive loading in the analog signal path; therefore, there is negligible speed overhead.
The supply voltage dependences of the delay time and the power consumption are shown in Figure 6.The power consumption is less than that of the conventional comparator (Figure 3).The delay time is maintained almost constant even when the supply voltage is decreased owing to the temporarily boosted technique.The delay time at the supply voltage of 0.5 V is 205 ps.A performance comparison between the conventional and proposed comparators is summarized in Table 1.The combination of a simple STAL and the body bias control calibration is also shown for comparison with the TB-STAL.The TB-STAL can successfully reduce the delay time.The delay time of the TB-STAL is less than half that discussed in Ref. [8] and its power consumption is less than that presented in Ref [8].The offset voltage after the calibration and the noise voltage of the TB-STAL are also sufficiently small for use in a 6-bit flash ADC.stacked analog latch is used as a comparator.The output of the comparator is latched to a set-reset latch (SR Latch) and the bubble correction is performed using a 3-input NAND circuit.Then, the binary code is generated through the gray and binary encoders.The body voltage (V calp and V caln ) for the offset calibration is generated by the calibration ladder and is selected by a selector.The gray and binary encoders are assigned as a pipeline stage; therefore, the total delay time of these circuits should be less than a cycle time.The forward body bias technique is applied to all the logic gates of the encoders to reduce the delay time.Moreover, a parallel binary encoder is used instead of a serial binary encoder.The serial and parallel binary encoders are shown in Figure 8.The serial binary encoder transforms a gray code into a binary code one by one.This configuration requires only five EXOR gates; however, a critical path has five stages.On the other hand, the parallel binary encoder has seven EXOR gates; however, the critical path has only three stages.The delay time can be reduced by approximately 30% using the parallel binary encoder.

Design of 6-Bit Flash ADC Using Proposed Comparator
The ADC output codes before and after the calibration are shown in Figure 9.The sampling and input frequencies are 1200 and 9.4 MHz and the supply voltage is 0.5 V.A Monte Carlo simulation including transient noise is performed, that is, the device mismatch and the noise are considered in the simulation results.A large error occurs due to the offsets in the comparators before the calibration, resulting in a poor signal to noise and distortion ratio (SNDR) of 17.9 dB.The body bias control calibration successfully improves the SNDR to 35.9 dB.The sampling frequency dependencies of the SNDR and spurious free dynamic range (SFDR) are shown in Figure 10.The input frequency is set to half the sampling frequency.The dashed lines show the simulation results under standard conditions and the solid lines show the simulation results after the calibration, including the device mismatch and the noise.The SNDR is almost constant up to 1.2 GHz and begins to degrade at more than 1.3 GHz.The SNDR and SFDR at the sampling frequency of 1.2 GHz are 34.0 and 39.4 dB.The input frequency dependencies of the SNDR and SFDR are shown in Figure 11.The sampling frequency is 1.2 GHz.The SNDR is almost constant even when exceeding the Nyquist frequency.The effective bandwidth is approximately 800 MHz.The power consumption breakdown at the sampling frequency of 1.2 GHz is shown in Figure 12.The total power consumption is 1.4 mW and approximately 50% is consumed in the comparators.A performance comparison with the current state-of-the-art technology is summarized in Table 2.The sampling frequency and the figure of merit (FOM) are greatly improved compared with that in the previous works at a supply voltage of 0.5 V [7] [8].The FOM is only 28 fJ/conv.-step,which is less than that of the SAR ADC when using 32-nm technology [14].

Conclusion
A low-voltage, high-speed flash ADC is designed.The most effective method for reducing the power dissipation of an ADC is the reduction of the supply voltage; however, simply reducing the supply voltage causes operating speed degradation.The bottleneck of the operation speed in a low-voltage region is the delay time increase of the comparator.The temporarily boosted comparator is proposed to address this problem.The proposed circuit only boosts the supply voltage in the comparison phase; therefore, it can reduce the delay time while keeping the power overhead to a minimum.Moreover, the body bias control calibration is combined with the temporarily boosted technique, which helps to create a low-power and high-precision comparator.A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique.The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and      Ref. [14] Ref. [7] Ref. [8] This work (MC + tran.noise sim.) an FOM of 28 fJ/conv.-stepeven at a low supply voltage of 0.5 V.

Figure 3 .
Figure 3. Simulated V DD dependence of delay time and power consumption of conventional comparator.

Figure 6 .
Figure 6.Simulated V DD dependences of delay time and power consumption.

Figure 9 .
Figure 9. ADC output codes before and after calibration.

Table 1 .
Performance comparison between conventional and proposed comparators.