Systematic Approaches of UWB Low-Power CMOS LNA with Body Biased Technique

This paper presents research on a low power CMOS UWB LNA based on a cascoded common source and current-reused topology. A systematic approach for the design procedure from narrow band to UWB is developed and discussed in detail. The power reduction can be achieved by using body biased technique and current-reused topology. The optimum width of the major transistor device M1 is determined by the power-constraint noise optimization with inner parasitic capacitance between the gate and source terminal. The derivation of the signal amplification S21 by high frequency small signal model is displayed in the paper. The optimum design of the complete circuit was studied in a step by step analysis. The measurements results show that the proposed circuit has superior S11, gain, noise figure, and power consumption. From the measured results, S11 is lower than −12 dB, S22 is lower than −10 dB and forward gain S21 has an average value with 12 dB. The noise figure is from 4 to 5.7 dB within the whole band. The total power consumption of the proposed circuit including the output buffer is 4.6 mW with a supply voltage of 1 V. This work is implemented in a standard TSMC 0.18 μm CMOS process technology.


Introduction
Ultra wide band (UWB) systems are a new wireless technology capable of transmitting data over a wide spectrum of frequency bands with very low power and high data rates.Among the possible applications, UWB technology may be used for imaging systems, vehicular and ground-penetrating radars, and communication systems.
In particular, it is envisioned that almost every cable at home or in an office will be replaced with a wireless connection that features hundreds of megabits of data per second [1].Although the UWB standard (IEEE 802.15.3a [2]) has not been completely defined, most of the proposed applications are allowed to transmit in a band between 3.1 -10.6 GHz.Two possible approaches have emerged to exploit the allocated spectrum.
One is the Direct-sequence UWB (DS-UWB) proposal.The DS-UWB proposal divides the whole band into two discontinuous bands with the lower band from 3.1 -4.85 GHz and the upper band from 6.2 -9.7 GHZ.The other is a proposal for a multiband orthogonal frequency-division multiplexing UWB (MB-OFDM UWB).The latter UWB proposal divides the whole band into 14 sub-bands 528 MHz that are grouped into five main bands [3].A low noise amplifier (LNA) is a critical building block of the receiver.For the full UWB LNA design goal, there are some factors that are required: sufficient gain and flatness, input/output matching, and most importantly, a low noise figure with a high signal to noise ratio (SNR) to enforce the sensitivity of the receiver.Low chip area and low power consumption are also desired for the LNA.In the past decade, many UWB LNAs with different topologies have been reported.Distributed amplifiers were popular circuits that had wideband characteristics [4]- [7].Since a distributed amplifier is a little more than cascaded stages, it requires large power consumption to add a common source amplifier [6].Of course, large chip size with extra inductors is another problem.
The resistive feedback topology with a narrowband inductively degenerated common-source amplifier is an area-saving solution for good input matching in the 3 -5 GHz UWB band [8].The feedback resistor R f may be lowered to reduce additional noise.If the g m of the transistor is raised, the Miller effect on R f will also be increased.Therefore, a higher current dissipation and larger MOS area are required [9]- [12].In recent years, the transformer as reactive feedback has been adopted for implementation of UWB application [13] [14].Moreover, low power CMOS LNA with transformer multicascode topology has been developed and reported for V-band and Q-band application [15].Some papers reporting on the common-gate amplifier have been suggested using wideband input matching as a solution by setting the input-transistor transconductance g m equal to the reciprocal of the source resistance [16]- [21].For this topology, high value of the transconductance contrasts with low-current dissipation.If the current-reused structure is added with this topology, lower power of the core circuit can be achieved under 5 mW without an output buffer [22].If the cascade stages are used in the circuit, it needs larger amounts of power for the ultra wideband RF receiver [23].However, with a common-gate configuration, it is hard to attain a 50 Ω real impedance for input matching and noise performance is also an area that requires improvement.
A common-source amplifier with a source degeneration inductor is one of the best approaches for narrowband application in terms of gain and noise performance [24].A common rule of this circuit for broadband matching application is obtained by replacing the gate inductance with a LC ladder network [14] [25] [26].A drawback of this approach for UWB is the large group-delay variation which means that the signal can experience several resonances in the input-matching network.If a series-peaking inductor is used with the gate of the second transistor, then the inductor L g2 can reduce the noise figure in the cascode structure with current-reuse topology [27].
The proposed circuit of a common-source amplifier with low power UWB LNA has been demonstrated [28].Additional analysis and discussion which emphasize the low power UWB are provided.Based on the effect of the body-biased technique and the current reused cascode structure, the low power consumption of our work can achieve lower than 5 mW including the output buffer.The analysis and design approach of the circuit is addressed in Section 2. The design procedure and body biased technique are also discussed in this Section 2. The measurement results are presented in Section 3. The conclusion is given in Section 4.

Proposed LNA Design Approach
The proposed low power LNA is shown in Figure 1.There are two stages including the core circuit of the first stage with common source (CS) amplifier M 1 and the buffer of the second stage.The first stage consists of the LC input matching network, body biased technique, and the cascode common source amplifiers M 1 and M 2 using the current-reused technique for low power design.The T-type LC filter is used for 50 Ω input matching and provides resonant frequency at 3 GHz for the high pass filter function.There are two transistors, M 1 and M 2 and both share the same drain current in a single path which saves power.The inductors L 3 and L 5 are used as the RF choke to avoid RF signal through the DC supply.A large value with L 3 = 9 nH and L 5 = 4 nH, respectively, is required.Inductor L 4 is used as the peaking inductor.Capacitor C 2 serves as the DC block capacitor and also builds up a RF signal path from transistor M 1 to transistor M 2 .Capacitor C 3 serves as the bypass capacitor and functions to make transistor M 3 as the ground state at the source node.The value for C 2 and C 3 are assumed to be C 2 = 2 pF and C 3 = 6 pF, respectively [29].In addition, using the body biased technique, the threshold voltage V T can be decreased by adjusting body voltage V B to reduce the power consumption, and enhance the gain performance during the cascode stage.To improve the gain flatness, a couple inductor L 6 is used.Finally, the source follower M 3 and the current source M 4 are used to as the output buffers.From the simulation, the measurements of our proposed circuit including the buffer are 4 mW and 4.6 mW, respectively.
We can develop a LNA design procedure of the common source with source inductor degeneration for narrowband application [30].
From the derivation of the power-constrained noise optimization, there are five steps necessary to complete the LNA design.
1) Determine the width of the optimum device M 1 from the equation that follows: where L is the length of transistor, R S is the resistance of source stage, Q SP is the quality factor of input stage and ω is the center frequency for which the design is made.
2) Bias the device with the amount of current allowed by the power constraint.
3) Select the value of source degenerating inductance to provide the desired input match.4) Compute the expected noise from the following equation: where γ is the thermal noise coefficient of transistor and α is the ratio of g m (α = g m /g d0 ), g d0 is the transconductance at zero bias voltage.5) Add sufficient inductance in the series with the gate to bring the input loop into resonance at the desired operating frequency.
From the former procedure, we can develop the optimum design for the UWB in a power constraint noise matching condition.

Determination of Transistor M1 and Input Matching
In the narrowband LNA circuit design, the optimum width of transistor M 1 can be calculated by Equation ( 1) under power constraint noise optimization.In the UWB LNA circuit design, if the bias drain current I D of the MOS device is initially set according to the power consumption requirement, then the noise can be estimated by Equation (2), and transistor M 1 also can be determined.For NMOS devices, the drain current at the saturated region can be indicated [31] ( ) where μ n is the mobility of electrons, C ox W is the total capacitance per unit length, L is the effective channel length and V GS − V TH is the overdrive voltage.From Equation (3), if channel length L and the overdrive voltage are kept at the constant, then the drain current is proportional to the capacitance.Since a MOSFET operating in saturation produces a current in response to its gate-source overdrive voltage, the transconductance gm can be expressed as the following: ( ) From Equation ( 6), g m represents the transconductance of the device, for a high g m , a small change in V GS results in a large change in I D .And it can be seen that g m decreases with the overdrive if I D is constant.The above descriptions from Equation (1) to Equation ( 6), the size of transistor M 1 is located at some range in the low noise figure from the power constraint.This phenomenon has been reporeted in the following papers [25] [32] [33] [34].However, these papers did not mention how to determine the size of transistor M 1 during the first stage which is an important factor to control the total noise figure of the circuit.Here, we adopted the power constraint noise optimization that accompanies with parasitic C gs of transistor M 1 to deal with the dimension of the size.In the circuit design, the multi fingers for layout profile are used for transistor to reduce the gate resistance (R g ) and noise figure for good behavior.
It is known that the parasitic capacitance is varied by the device size in the high frequency region.If gate resistance R g is considered and is assumed, then the input impedance Z in can be obtained as the following Equation ( 7): where s is equal to j2πf.As described above, if the budget of power consumption is determined, then the noise figure and the range of the M 1 device size are also obtained as shown in Figure 2.
Based on the power constraint noise matching, the noise figure is raised with drain current being decreased as shown in Figure 2. If the noise figure is properly chosen by an average value of 3.5 dB in the whole band, then a transistor size from 75 µm to 150 µm is preferred.If the parasitic capacitance of transistor M 1 is viewed as a part of the input for the impedance matching network, then the transistor size can be optimized for input matching in the whole band.Figure 3 shows the S 11 of the input impedance matching with different transistor sizes.If  the width of the device is 100 µm, the locus of S 11 must be improved in the low band.On the contrary, if the width of the device is larger than 160 µm, then the locus of S 11 must be improved in the high band.Therefore, the better transistor width is close to 130 µm as shown in Figure 3 and also is the width chosen for our proposed circui.

Analysis of Source Inductor Degeneration
In the single band or narrow band low noise amplifier, the S 11 of a common source with inductive degeneration is better than without inductive degeneration.This principle is also fitted to ultra wideband LNA.
The input impedance of the common source inductor L s included in the circuit can be modified from Equation (7) as follows: ( ) Here g m1 is the transconductance of transistor M 1 , then, owing to the contribution of L 2 , the locus of S 11 is different from the one in which we omitted L s in the circuit for input matching.This phenomenon can be seen in  we must check the effects of gain and the noise figures.
From Figure 5(a), the noise figure with source inductor is 3 -4.7 dB and without source inductor it is 3 -4.1 dB, respectively.From Figure 5(b), the forward gain with source inductor is 11.3 -12.1 dB and without source inductor it is 11.7 -12.9 dB, respectively.For the proposed circuit, first, the number of inductors must be decreased to decrease chip size.Second, input matching for the whole band must be done.Third, it is necessary to avoid the generation of thermal noise sources with a parasitic resistor.
Finally, whether the source inductor is adopted or not in the circuit for wideband application, there is a little difference of performance from the effect of gain or noise figure.So the source inductor is omitted to save the chip size in our proposed circuit.The detail usage of source inductor is more described in the references [34].

Analysis of Current Reused Stage and Output Buffer
Cascode topology is commonly used to save power and for high gains with a fixed supply voltage application.Recently, the current reused structure has been popularly adopted [27] [32] [35].The first stage (C 1 , C 2 , L 1 , L 2 , M 1 ) is designed to resonate at the lower band, and the second stage (R 1 , L 4 , L 5 , M 2 ) is designed to resonate at the higher band.
For RF signal analysis, the forward gain A v from signal source V sig to output voltage V out can be expressed as the following Equation ( 9): where A V1 is the gain of transistor M 1 , A V2 is the gain of transistor M 2 and A V3 is the gain of transistor M 3 , respectively.The detailed derivation can be seen in the appendix.The output resistance R out is approximated with a low frequency model as in Equation (10): When g m3 is the transconductance of transistor M 3 , r o3 and r o4 are the output resistance of transistors M 3 and M 4 , respectively.For UWB application, the inter stage inductor L 6 can resonate with the parasitic capacitor (C gs3 ) of transistor M 3 which creates gain peaking at the high frequency band at about 11 GHz.Of course, it also provides the best gain flatness of the proposed circuit.For achieving good gain flatness, the optimization value of L 6 and L 4 are 2.93 nH and 0.48 nH, respectively.

Analysis of Body Biased Technique
The body biased technique is not used for designing in traditional electronic circuitry with respect to body effect.Recently, self forward body bias and adaptive body bias have been adopted to design circuits that use less power in narrow band considerations [29] [36]- [38].The wideband and UWB LNA are even reported in the following references [28] [39] [40].
Since the standard CMOS process is without a multiple gate oxide option, the threshold voltage V T can be calculated by adjusting with V SB as shown in Equation ( 11): where V SB is the source to body voltage, V T0 is the threshold voltage for V SB = 0, γ is a process dependent parameter, and F φ is a semiconductor parameter with a typical value in the range of 0.3 to 0.4 V.
There are two models to understand the body bias technique with analytical expression of the circuit.1) Body effect analog modeling First, assuming BS F V φ  which is the "small signal" approach, and by applying the Taylor series to expression (11), we obtain Equation (12).
This Equation ( 12) highlights a linear relationship between the threshold voltage of the MOS transistor and the potential applied to its bulk.
2) DC mode The MOS drain current is given by: For a given V GS , I D current flowing through the MOS transistor depends on bulk-to-source voltage.Hence, transistor biasing can be controlled thanks to the body effect in a DC approach.However, one has to pay attention to the fact that the V SB range is limited.Indeed, if the V T enhancement induces no significant parasitic constraint on DC characteristics despite the current decrease, the reduction of the threshold voltage can disturb the transistor effect.
Assuming that V SB is lower than roughly speaking 0.7 V, the bulk-to-source PN junction of the NMOS transistor is thus forward biased, producing a leakage current and aborting the transistor functionality.It sets up the limit whose body effect is useful to implement a function thanks to the DC approach.To use body bias NMOSFET, a deep Nwell process is needed.In addition, a deep Nwell process can reduce noise cross-talk through the substrate [39].
This circuit design with body bias technique allows for a reduction in power consumption.A 0.45 V body bias is used to make the transistors in the strong inversion region.It can be seen from Figure 6(a) that the transistor with 0.45 V body bias enters the strong inversion region, while the one with 0 V body bias is still in the weak inversion region.
The gain and NF of the LNA are drawn versus V BS as shown in Figure 6(b).The reduction of body bias implies a current decrease thus lessening both gains and noise figures.Therefore, we set V BB = 0.45 V. Practically, the forward body voltage is limited to 0.4 -0.7 V.
To further investigate the influence of the bias conditions on the noise figure (NF), the simulated values versus gate to source voltage (V GS ) for the different body bias voltages are demonstrated in Figure 6(c), which provides the design guidelines of the LNA.The cross section region with optimum values are preferred, the voltages of V GS and V BS are as low as good for low power design.Therefore, the voltage V G is chosen as 0.55 V.
However, how much power can be reduced by the body biased technique is still uncertain.In the circuit, if the parameter gain and S 11 are in the same condition, then without body bias, the simulation of power consumption in the core circuit is 4.44 mW for 1.2-V supply voltage and 7.23 mW including the output buffer.With body bias, the simulation of power consumption in the core circuit is 3.24 mW and 4.1 mW including the output buffer.The measurement of the power consumption is 3.32 mW and 4.6 mW including the output buffer.

Measurement
Figure 7 shows the die photo of the UWB LNA with the body bias technique, which has a chip size of 0.928 mm 2 .In Figure 8 it can be seen that the input return loss (S 11 ) is lower than −12 dB, but in Figure 9, it can be seen that the output return loss (S 22 ) is lower than −14 dB from 3.1 GHz to 10.6 GHz, respectively.The power gain, whose peak value is 13 dB, is shown in Figure 10.In Figure 11, it can be seen that the noise figure is 4 dB -5.7 dB from 3.1 GHz to 10.6 GHz with a 1 V supply voltage.In Figure 12, the third-order input intercept point (IIP 3 ) is −14 dBm.The total power consumption is 4.6 mW at 1 V supply voltage.
To compare the overall performance of our LNAS with previously published ones, a figure of merit (FOM) that takes into account the gain, NF, BW, IIP 3 , and the DC power consumption of the LNA is defined as [41] [42] Where BW is the bandwidth, P D is the power consumption in milliwatts, the values of gain and noise factor F are their absolute values, IIP 3 is indicated as linearity of the amplifier or circuit, and also called the input third-order intercept point.
The comparison of the proposed work with other reported papers are shown in In general case of low noise amplifier, most of the circuit design did not consider the linearity characterization.The linearity has a serious effect on the power amplifier.Therefore, we can show that our performance of FOM is better than others, and FOM _IIP3 is fairly good but still not the optimal choice.

Conclusion
In this paper, a UWB low noise amplifier with body bias technique has been presented.The proposed body bias technique is employed to achieve low power consumption.The T-type matching network used for input matching to achieve gain flatness and frequency bandwidth.The power consumption is as low as 4.6 mW with a 1 V supply voltage.From 3.1 to 10.6 GHz, the maximum power gain is 13 dB and the minimum noise figure is 4 dB.
( ) ( ) ( ) ( ) In the circuit, analysis of the high frequency models always meets the Miller's theorem.The ratio of drain to gate node with transistor M 1 is by . Transistor M 2 is also simply expressed as .Therefore, K 1 and K 2 can be obtained in equations ( 13) and ( 14), respectively.Finally, we can get the total overall gain of the complete circuit in Equation (1).

Figure 2 .
Figure 2. Relation between noise figure and drain current of transistor M 1 .

Figure 4 .
With or without inductor L s , they both have good S 11 lower than −10 dB in the whole band.Of course,

Figure 4 .
Figure 4.The simulation of S 11 with/without L s .

Figure 6 .
Figure 6.(a) Simulation I D and V G characteristics of a NMOS transistor with forward body bias; (b) Characteristics of the power gain and noise verse V BS ; (c) Simulation NF and I D of the MOSFET with a fixed V DS of 1 V for the different body bias.

Figure 7 .
Figure 7. Layout of the proposed UWB LNA with body bias technique.

Figure 8 .
Figure 8. Measured and simulated S 11 of the fabricated LNA.

Figure 9 .
Figure 9. Measured and simulated S 22 of the fabricated LNA.

Figure 10 .
Figure 10.Measured and simulated S 21 of the fabricated LNA.

Figure 11 .
Figure 11.Measured and simulated NF of the fabricated LNA.

Table 1 .
Our work shows high

Table 1 .
Measured comparison of the proposed 3.1 -10.6 GHz.