New Analysis to Measure the Capacitance and Conductance of MOS Structure toward Small Size of VLSI Circuits

In this research thin film layers have been prepared at alternate layers of resistive and dielectric deposited on appropriate substrates to form four terminal R-Y-NR network. If the gate of the MOS structures deposited as a strip of resistor film like NiCr, the MOS structure can be analyzed as R-Y-NR network. A method of analysis has been proposed to measure the shunt capacitance and the shunt conductance of certain MOS samples. Mat lab program has been used to compute shunt capacitance and shunt conductance at different frequencies. The results computed by this method have been compared with the results obtained by LCR meter method and showed perfect coincident with each other.


Introduction
In recent years, there have been rapidly growing interest and activity in thin film integrated circuits as an approach to microelectronics.Electronic circuits have been fabricated on the basis of replacing conventional lumped elements with their thin film equivalents.Essentially the VLSI memory devices are Electronic structures.The Metal-Oxide-Silicon (MOS) structures are an important type of the VLSI memory devises.MOS capacitance is one of the key test structures for VLSI technology characterization.It permits the determination of the electrical characteristics of a given technology such as oxide thickness, substrate doping, the switching speed and the driving capability of VLSI circuits [1].
The MOS capacitor is a Metal-Oxide-Semiconductor structure.Figure 1 show the MOS capacitor which consists of few layers: semiconductor substrate with a thin oxide layer and a top metal contact also referred to as the gate.A second metal layer forms an ohmic contact to the back of the semiconductor, also referred to as the bulk.The electrical characteristics of MOS structures determine the switching speed of VLSI circuits.The electrical characteristics of MOS structures may be estimated using few simple formulas, such [2]: The gate capacitance: The channel resistance: R C = R s (L/W).Where R s is the sheet resistance, C ox is the oxide capacitance, L is the channel length and W is the channel width.Unfortunately MOS is not simple and computing the channel resistance and gate capacitance is more complicated.
As MOS feature size is getting smaller and smaller, the thickness of layers becomes more and more significant.The correct extraction of parasitic capacitance and resistance in deep submicron VLSI design is getting a major research area.The MOS different modes of operation, namely accumulation, flat band, depletion and inversion [3] are introduced here.The MOS structure has a p-type substrate.The structure will be referred as an n-type MOS capacitor since the inversion layer as discussed below contains electrons.
To understand the different bias modes of an MOS capacitor three different bias voltages were considered.The first one is below the flat band voltage, V FB , a second between the flat band voltage and the threshold voltage V T , and finally one larger than the threshold voltage.
These bias regimes are called the accumulation, depletion and inversion mode of operation.These three modes as well as the charge distributions associated with each of them are shown in Figure 2.
Accumulation occurs typically for negative voltages where the negative charge on the gate attracts holes from the substrate to the oxide-semiconductor interface.Depletion occurs for positive voltages.The positive charge on the gate pushes the mobile holes into the substrate.Therefore, the semiconductor is depleted of mobile carriers at the interface and a negative charge, due to the ionized acceptor ions, is left in the space charge region.The voltage separating the accumulation and depletion regime is referred to as the flat band voltage, V FB .Inversion occurs at voltages beyond the threshold voltage.In inversion, there exists a negatively charged inversion layer at the oxide-semiconductor interface in addition to the depletion-layer.This inversion layer is due to minority carriers, which are attracted to the interface by the positive gate voltage.The majority of the up-dated work however has been concerned with the investigation of sandwiched three layer rectangular and exponential shaped structures.In  these structures, alternate layers of resistive and dielectric films are deposited on appropriate substrates to form four terminal R-Y-NR networks [4], which is a special type of MOS structure.In this research a new method to measure the capacitance and conductance of MOS structures was derived and discussed.The method of analysis that was used to obtain the steady state ac response and the response to a unit step is rather straightforward.It is shown that the partial differential equation relating voltage, position, and time is of second order homogeneous ordinary linear differential equation [5].If the MOS gate deposited as a strip of resistor film like NiCr, MOS structure can be analyzed as R-Y-NR network [6].

Open Circuit Voltage Transfer Function
The matrix parameter functions (MPFs) of a solvable DP R-Y-NR network are defined with the following symbols [5]:   Employing the technique of sub network generation [7,8], the open circuit voltage transfer function T vo of the exponential distributed parameter two-port three Layer sub networks of Figure 4  The open circuit voltage transfer function [7] for the Sub network in Figure 4(a) is: And that for the sub network in Figure 4(b) is: where g and a are (MPFs) for the exponential distributed parameter (DP) R-Y-NR structure.For structure of length L and ac signal, they are identified as [8]:  For N = 0 which means that the second resistive layer is perfect conductive film, Equations ( 7) and ( 8) will respectively be abbreviated to: For N = 0 which means that the second resistive layer is perfect conductive film, Equations ( 7) and ( 8) will respectively be abbreviated to: From Figure 4(a): From Figure 4(b): Substituting the matrix parameter functions in the Equations ( 11) and (12) will respectively give: From Figure 4(a): From Figure 4(b): Considering the uniform distributed thin film R-Y-NR network; that means the constant of exponential taper is zero (K = 0), and substituting in the Equations ( 13) and ( 14) leads respectively to get: From Figure 4(a): From Figure 4(b): where m is a complex angle per unit length and Then the complex angle is mL = m × L and

Experimental Results
Let For sake of showing accuracy of the proposed method, shunt capacitance and shunt conductance measurements have been carried out on a certain MOS samples.These samples are accomplished by depositing a strip of NiCr resistor thin film as a gate contact and then depositing two dot aluminum points at the two ends of the strip for measurement purposes.And: Subtracting (20) from ( 19) and manipulating the results lead to: And hence: From Equation (18): Joining Equations ( 21) and ( 22) gives: At the beginning, transfer function of the device has been measured for both configurations shown in Figure 4. Response of transfer function magnitude and its phase with respect to frequency have been plotted as shown in Figures 5 and 6 respectively for positive gate biasing.For negative biasing, transfer function magnitude and phase responses have been plotted as shown in Figures 7  and 8 respectively.Mat lab program has been used to compute shunt capacitance and shunt conductance for strip gate MOS structure at different frequencies.For a zero bias, shunt capacitance and shunt conductance of the MOS structure at different frequencies have been computed.The computed results and the results obtained using LCR meter method [9] have been plotted, as shown in Figures 9 and 10.It is clear that the results obtained from the two methods coincided with each other.

Conclusions
In this research the high frequency C-V and G-V device measurements were fulfilled using MOS structure as a      thin film distributed R-Y-NR structure with four terminal two port network.This conclusion encourage using the proposed method as a tool for C-V and G-V plots at any frequency.

Figure1.
Figure1.Schematic cross section of the MOS.

Figure 3
represents a typical C(V) behavior for a MOS capacitance test structure, measured at high frequency (1 MHz).The operation ranges are also indicated on this figure: strong inversion, depletion, and accumulation.

Figure 2 .
Figure 2. The three bias regimes of MOS structures.

Figure3.
Figure3.C(V) behavior for a MOS capacitance test structure measured at high frequency (1 MHz).

Figure 5 .
Figure 5. Transfer function magnitude frequency response of a strip gate MOS device for different positive biases.

Figure 6 .
Figure 6.Transfer function phase frequency response of a strip gate MOS device for different positive biases.

Figure 7 .
Figure 7. Transfer function magnitude frequency response of a strip gate MOS device for different negative biases.

Figure 8 .
Figure 8. Transfer function phase frequency response of a strip gate MOS device for different negative biases.

Figure 9 .
Figure 9.Comparison between capacitance determined by the two methods for zero bias.

Figure 10 .
Figure 10.Comparison between leakage conductance dedetermined by the two methods for zero bias.
is obtainable in terms of the matrix parameter functions (MPFs).