A Very Low Level dc Current Amplifier Using SC Circuit : Effects of Parasitic Capacitances and Duty Ratio on Its Output

This paper describes a very low level dc current amplifier using switched capacitor (SC) circuit to miniaturize and improve its output response speed, instead of the conventionally used high-ohmage resistor. A switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier. The simulation results show that the parasitic capacitances that are distributed to the input portion of the amplifier have some effect on offset voltage. From the experimental results, it is seen that the duty ratio of the clock cycle of SC circuit should be in the range from 0.05 to 0.70. It is suggested that the proposed very low level dc current amplifier using SC circuit is an effective way to obtain both a faster output response and its miniaturization.


Introduction
When very small currents are measured by mass spectroscopes and radiation detectors, response speeds of the measuring instruments are limited by those of very low level dc current amplifiers [1].This means that the amplifiers are required to observe rapid transient phenomena.In general, the very low level dc current amplifier for measuring small currents consists of an amplifier having high input impedance and a high-ohmage negative feedback resistor.The amplifier with high-ohmage resistor has unavoidable effects of the stray capacitances across its terminals.This factor causes the amplifier to have a complicated frequency characteristic, which results in its poor responses [1] [2].Some shielding techniques [3]- [5] have been reported for the purpose of de-creasing these capacitive components.In spite of the fact that these methods have been employed, it is difficult to realize drastic improvements of the response speeds of the very low level dc current amplifier.Neither are the amplifiers with shielding methods appropriate for miniaturization.A positive feedback circuit [6] had also been used as another approach to decreasing the stray capacitances.The amplifier with the positive feedback circuit however is unstable and begins to oscillate in this case.The resultant high speed response of the amplifier has not been achieved so far.
In this paper, an amplifier with switched capacitor (SC) circuit and offset controller are proposed.The SC circuit is equivalent to a resistor and is suitable for miniaturization.We investigated how much effect parasitic capacitances in the SC circuit have on the amplifier's output.Furthermore, effect of duty ratio of the clock cycle on the output of the amplifier was experimentally demonstrated.

Circuit Description
Figure 1 depicts a very low level dc current amplifier, including SCF and a small current source.g C , g R and K are the input capacitance, input resistance, and amplification factor of the amplifier having a high input re- sistance, respectively.As an input signal to the amplifier in our experiment, we utilize a triangular wave voltage produced by the function generator g V and the differentiating capacitor s C (reactance attenuator) to obtain a square wave current s I with a high output impedance.o C is the output capacitance to the ground of s C .The input stage of the offset controller is composed of a JFET which has much higher input impedance than the negative feedback circuit has.Its voltage drift is very small (several μV).Therefore, the offset controller does not have much effect on the current detection sensitivity of the amplifier.The SC negative feedback circuit and SCF are shown in Figure 1

Equivalent Resistance of SCNF
From Figure 1(b), the voltage at node b , b V , is given by and an electric charge 1 q at 1 C is ( ) From Equation (1) and the relationship that - , the electric charge 1 q at 1 C can be rewritten as ( ) for 1 K  .The quantity of the charge that is transported from node a to node b is equivalent to 1 q because (a) (b) the electric charge 1 q at 1 C during 2 T is totally discharged.Thus, a current, I , flowing from node a into node b during one clock cycle s T is ( ) Since the current to be measured in the amplifier s I flows into the SC circuit, s I I = .From the relationship that o feq s V R I = , the equivalent resistance of SC negative feedback circuit feq R is represented by ( ) while the equivalent SC resistance [7] sc R becomes where s f is the clock frequency.The attenuation factor of the attenuator x [8] is given by ( ) Thus, from Equations ( 4) to ( 6), feq R can be obtained as It is observed from Equation ( 6) that x is dependent on the ratio of capacitances of 2 C and 3 C .

Theoretical Output Voltage of the Amplifier
The equivalent SC negative feedback circuit is illustrated in Figure 2(a).It is seen from Equations ( 5) and ( 7) that the SC negative feedback circuit is equivalent to the capacitor of where ω is the angular frequency.The input admittance of the very low level dc current amplifier in Y is ( )   8), a simplified input equivalent circuit of the very low level dc current amplifier using SC circuit can be drawn as shown in Figure 2(c).
An enlarged input voltage waveform of the amplifier at the positive final steady-state, i V , is illustrated with the help of clock waveform in Figure 3 ( ) Since electric charges of the SC circuit are conserved just before and after s t nT = , the following equation is obtained The input voltage just before .
From Figure 3 and Equation ( 10), the voltage m V is From Equations ( 9) and ( 11), the input voltage just after .
The resultant peak voltage Substituting Equation (12) into Equation (13) gives the following equation: Therefore, the peak output voltage of the amplifier during 1 T , 1 op V , can be written as .
It is found from Equation (15) that the theoretical output voltage of the very low level dc current amplifier using SC circuit can be obtained by sampling 1 op V .In this paper, the SCF is used to sample 1 op V from the output voltage of the very low level dc current amplifier using SC circuit for the following reasons.Using a sampleand-hold circuit generally requires a clock generator that completely differs from two non-overlapping clock signals utilized by the SC negative feedback circuit.Using a low-pass filter provides for not theoretical output voltage, but approximately half amplitude of output voltage of the amplifier at a final steady-state.On the other hand, using the SCF with the SC circuit allows for sharing the two non-overlapping clock signals.In addition, both the SCF and SC circuit can be manufacturable by the same process.We are easily available to miniaturize SC circuits using IC-compatible techniques.Therefore, the SCF is useful from the viewpoint of miniaturization.

Effect of Parasitic Capacitances the Amplifier's Output
To evaluate response speed of the very low level dc current a square wave current s I with a time period of 5 ms and an amplitude of 10 nA was input to the amplifier.K and g C were set to 1300 and 17 pF, respectively.We fixed the equivalent SC resistance RC R of 1 MΩ using 1 C of 10 pF and s f of 100 kHz.The attenuation factor x of 1/100 was also set using both 2 C of 1000 pF and 3 C of 9.3 pF.The total equivalent resistance feq R of the SC negative feedback circuit was 100 MΩ.The duty ratio d of 0.5 was used.A switch model [9] used in the computer simulation is shown in Figure 4.The symbols D , G , and S stand for drain, gate, and source of MOS-FETs.Assuming that parasitic capacitances between two terminals exist, as shown in Figure 4(a) and Figure 4(b), each analog switch composed of a combination of an nMOS and pMOS was used (see Figure 4(c)).Transient analyses of the very low level dc current amplifier using SC circuit were carried out using the electronic circuit simulator PSpice (Cadence Design System, Inc.).Table 1 lists the parasitic capacitance values determined by trial and error.

Effect of Duty Ratio on the Amplifier's Output
The amplification factor K of the very low level dc current amplifier using SC circuit shown in Figure 1 was set to 62.3 dB.Its output waveform was observed using an oscilloscope.Since the triangular wave voltage, which had a time period of 10 ms and an amplitude of 10 V, was differentiated by the differentiating capacitor s C of 1.25 pF, a square wave current with a time period of 10 ms and an amplitude of 10 nA was obtained as an input current s I to the amplifier.As switches for the SC circuit and SCF, we used CMOS analog switches   C , and then the attenuation factor of the attenuator x was set to 1/100 by adjusting capacitance of 3 C .Referring to Equation ( 7), the total equivalent resistance of the SC circuit became 100 MΩ.An offset volt- age controller, which was connected to the input of the amplifier and had a gain of unity, was also used to cancel the offset voltage in our experiment.

Effect of Parasitic Capacitances on the Amplifier's Output
First, based on the assumption that nMOS has exactly the same parasitic capacitances as pMOS has, transient analyses of the amplifier were done.Figure 5 shows the simulation result with the parasitic capacitances shown in Table 1.It can be observed that the output waveforms of the amplifier have vibrations that cause black area due to charge and discharge actions of the SC negative feedback circuit (see Figure 5(a) and Figure 5(b)).Thus, it is difficult to measure an input current from them.Calculating average values of 1 op V from 10.0 ms to 12.5 ms and from 12.5 ms to 15.0 ms in Figure 5(a), they are respective +1.0 V and -1.0 V. From Equation (15), output voltage of 1 V should be obtained as the theoretical output of the amplifier.The output waveform of the SCF, o V ′ , is shown in Figure 5(c).In this case, the peaks of the output voltage during 1 T were sampled by the SCF.As generally defined, the rise time is the time required for the output waveform to rise from 10% to 90% of its final steady-state value.The rise time of the output waveform of the SCF is 10.3 μs, while that of the amplifier using conventionally used high-ohmage resistor is 83.8 μs [10].It is seen from   SCF considerably reduces vibrations as well as unnecessary components, and that the input current s I can be obtained by measuring the amplitude of its output voltage.
Secondly, we also performed computer simulations with an addition of 0.5 pF to each parasitic capacitance of nMOS or pMOS listed in Table 1 to find out which parasitic capacitance would have effect on the output of the amplifier.

Effect of Duty Ratio on the Amplifier's Output
Experimental results are shown in Figure 6.In the experimental result with the duty ratio of 0.05 d = , the output amplitude of the amplifier is larger than 1 V.It is also observed that the output waveform at positive and negative final steady-states is rather distorted.On the other hand, in that of 0.70 d = , the amplitude becomes smaller than 1 V.It is found from the experimental results that the duty ratio of the clock cycle should be in the range: 0.05 0.70 d < < . Using duty ratios larger than 0.70 leads to output waveform degradation.It is thought that the longer 1 T (the shorter d ) we use, the more stable output waveform can be sampled using the SCF.Finally, a relationship between the clock frequency s f and error rate of feq R was investigated.Setting s f and 2 C to respective 100 kHz and 1000 pF, we adjusted both capacitances of 1

Conclusion
It is found from the simulation results that the parasitic capacitive components that are distributed close to the input portion of the amplifier have effect on the offset voltage.The experimental results show that the duty ratio of the clock cycle has an effective range.The error rate of less than 3.0% in feq R is also obtained in our experiment.These results suggested that the proposed amplifier using SC circuit would provide the measuring device having better properties of both faster response and downsizing.
Figure1depicts a very low level dc current amplifier, including SCF and a small current source.g C , g R and K are the input capacitance, input resistance, and amplification factor of the amplifier having a high input re- sistance, respectively.As an input signal to the amplifier in our experiment, we utilize a triangular wave voltage produced by the function generator g V and the differentiating capacitor s C (reactance attenuator) to obtain a square wave current s I with a high output impedance.o C is the output capacitance to the ground of s C .The input stage of the offset controller is composed of a JFET which has much higher input impedance than the negative feedback circuit has.Its voltage drift is very small (several μV).Therefore, the offset controller does not have much effect on the current detection sensitivity of the amplifier.The SC negative feedback circuit and SCF are shown in Figure1(b).The former circuit is composed of a basic SC circuit and a feedback rate attenuator.The switches in Figure1(b) are controlled by two non-overlapping clock signals.The switch 11 S is syn- chronous with 12 S and 13 S .21 S is synchronous with 22 S , 23 S and 24 S .The switches 31 S and 32 S in the SCF are synchronous with 11 S and 21 S , respectively.

1 xC
and four switches 11 S , 13 S , 21 S , and 24 S .The equivalent circuit of the very low level dc current amplifier is shown in Figure 2(b).The box la- beled "SC" in Figure 2(b) stands for the SC negative feedback circuit.The figure shows that the equivalent SC negative feedback circuit is connected with the equivalent circuit of the amplifier at the terminals between nodes a and c.Applying Millman's theorem to Figure 2(b), the input voltage i V is represented by

Figure 2 .
Figure 2. Equivalent circuits of (a) SC negative feedback circuit and (b) very low level dc current amplifier.(c) shows simplified input equivalent circuit of (b). xC1

Figure 3 .
Figure 3. Relationship between enlarged input voltage and clock waveform.

Figure 4 .
Figure 4. Switch model used in PSpice simulation.Configurations of (a) nMOS, (b) pMOS FET models with parasitic capacitances, and (c) CMOS switch.

Figure 5 Figure 5 .
Figure 5. Simulation results with parasitic capacitances shown in Table 1.(a) Output waveform of very low level dc current amplifier using SC circuit; (b) its enlarged waveform at a positive final steady-state; and (c) output waveform of SCF.The rise time in (c) is 10.3 µs.

Figure 7 .Table 2 .
Figure 7. Relationship between the clock frequency s f and error rate of feq R (x = 1/100).
f s[kHz]

negative feedback circuit Offset Controller SCF Vo Vo' K Vi Cg Co Cs Vg Is Rg 1 basic SC circuit feedback rate attenuator SCF S 31 S 32 C t C h S 24 S 23 C 3 C 2 C 1 S 21 S 22 S 12 S 11 V i V o V ' o S 13 a b c
-SC 1 s T is the clock cycle of the switches.1T,2T and d are ( ) m V , is

Table 1 .
Parasitic capacitance values based on the assumption that nMOS and pMOS have the same parasitic capacitive components.MAXIM Integrated Products, Inc.) having the maximum leakage current of 10 pA.Further, variable capacitors 1 C and 3 C were utilized.Parasitic capacitances of analog switches have some effect on equivalent resistance of the SC negative feedback circuit feq R , which causes errors in feq R of the amplifier.Thus, the equivalent SC resistance sc R with the clock frequency s f of 100 kHz was set to 1 MΩ by adjusting capaci- tance of 1

Table 1 .
(a) Output waveform of very low level dc current amplifier using SC circuit; (b) its enlarged waveform at a positive final steady-state; and (c) output waveform of SCF.The rise time in (c) is 10.3 µs.

Table 2
summarizes parasitic capacitances that have effect on offset voltage of the amplifier.For example, all the cases in the switch 11 On the other hand, parasitic capacitances that are not listed in Table2do not have effect on its output voltage.From the simulation results, it is found that differences between value of dg n C − and that of of the amplifier, and that parasitic capacitive components that are distributed close to the amplifier's input portion are deeply related to it.